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| this is information on a product in full production. september 2014 docid025938 rev 4 1/119 stm32l051x6 stm32l051x8 access line ultra-low-power 32-bit mcu arm ? -based cortex ? -m0+, up to 64 kb flash, 8 kb sram, 2 kb eeprom, adc datasheet - production data features ? ultra-low-power platform ? 1.65 v to 3.6 v power supply ? - 40 to 125 c temperature range ? 0.27 a standby mode (2 wakeup pins) ? 0.4 a stop mode (16 wakeup lines) ? 0.8 a stop mode + rtc + 8 kb ram retention ? 139 a/mhz run mode at 32 mhz ? 3.5 s wakeup time (from ram) ? 5 s wakeup time (from flash) ? core: arm ? 32-bit cortex ? -m0+ with mpu ? from 32 khz up to 32 mhz max. ? 0.95 dmips/mhz ? reset and supply management ? ultra-safe, low-power bor (brownout reset) with 5 selectable thresholds ? ultralow power por/pdr ? programmable voltage detector (pvd) ? clock sources ? 1 to 25 mhz crystal oscillator ? 32 khz oscillator for rtc with calibration ? high speed internal 16 mhz factory-trimmed rc (+/- 1%) ? internal low-power 37 khz rc ? internal multispeed low-power 65 khz to 4.2 mhz rc ? pll for cpu clock ? pre-programmed bootloader ? usart, spi supported ? development support ? serial wire debug supported ? up to 51 fast i/os (45 i/os 5v tolerant) ? memories ? up to 64 kb flash with ecc ?8kb ram ? 2 kb of data eeprom with ecc ? 20-byte backup register ? sector protection against r/w operation ? rich analog peripherals ? 12-bit adc 1.14 msps up to 16 channels (down to 1.65 v) ? 2x ultra-low-power comparators (window mode and wake up capability, down to 1.8 v) ? 7-channel dma controller, supporting adc, spi, i2c, usart, timers ? 7x peripherals communication interface ? 2x usart (iso 7816, irda), 1x uart (low power) ? 2x spi 16 mbits/s ? 2x i2c (smbus/pmbus) ? 9x timers: 1x 16-bit with up to 4 channels, 2x 16-bit with up to 2 channels, 1x 16-bit ultra-low-power timer, 1x systick, 1x rtc, 1x 16-bit basic, and 2x watchdogs (independent/window) ? crc calculation unit, 96-bit unique id ? all packages are ecopack ? 2 table 1. device summary reference part number stm32l051x6 stm32l051c6 stm32l051k6 stm32l051r6 stm32l051t6 stm32l051x8 stm32l051c8 stm32l051k8 stm32l051r8 stm32l051t8 ufqfpn32 5x5 mm lqfp32 7x7 mm lqfp48 7x7 mm lqfp64 10x10 mm & " ' ! wlcsp36 tfbga64 5x5mm www.st.com
contents stm32l051x6 stm32l051x8 2/119 docid025938 rev 4 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.2 ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3 arm? cortex?-m0+ core with mpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4 reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.1 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.2 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4.4 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5 clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.6 low-power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 24 3.7 general-purpose inputs/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.8 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.9 direct memory access (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.10 analog-to-digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.11 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.11.1 internal voltage reference (v refint ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.12 ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 27 3.13 system configuration controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.14 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.14.1 general-purpose timers (tim2, tim21 an d tim22) . . . . . . . . . . . . . . . . 28 3.14.2 low-power timer (lptim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.14.3 basic timer (tim6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.14.4 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.14.5 independent watchdog (iwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.14.6 window watchdog (wwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 docid025938 rev 4 3/119 stm32l051x6 stm32l051x8 contents 4 3.15 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.15.1 i2c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.15.2 universal synchronous/asynchronous receiver transmitter (usart) . . 31 3.15.3 low-power universal asynchronous receiver transmitter (lpuart) . . . 31 3.15.4 serial peripheral interface (spi)/inter-integrated sound (i2s) . . . . . . . . 32 3.16 cyclic redundancy check (crc) calculation unit . . . . . . . . . . . . . . . . . . . 32 3.17 serial wire debug port (sw-dp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.3.2 embedded reset and power control bloc k characteristics . . . . . . . . . . . 51 6.3.3 embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.3.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.3.5 wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.3.6 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.3.7 internal clock source charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3.8 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.3.9 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.3.10 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.3.11 electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3.12 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3.13 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3.14 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 contents stm32l051x6 stm32l051x8 4/119 docid025938 rev 4 6.3.15 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3.16 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3.17 comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3.18 timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.3.19 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.1.1 lqfp32 7 x 7 mm low profile quad flat package . . . . . . . . . . . . . . . . . . 98 7.1.2 ufqfpn32 5 x 5 mm package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.1.3 lqfp48 7 x 7 mm low profile quad flat package . . . . . . . . . . . . . . . . . 104 7.1.4 lqfp64 10 x 10 mm low profile quad flat package . . . . . . . . . . . . . . . 107 7.1.5 wlcsp36 0.4 mm pitch wafer-level chip scale package . . . . . . . . . . . 110 7.1.6 tfbga64 5 x 5 mm thin profile fine pitch ball grid array package . . . . 111 7.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 7.2.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 docid025938 rev 4 5/119 stm32l051x6 stm32l051x8 list of tables 6 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. ultra-low-power stm32l051x6/x8 device features and peripheral counts. . . . . . . . . . . . . 11 table 3. functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 16 table 4. cpu frequency range depending on dynamic voltag e scaling . . . . . . . . . . . . . . . . . . . . . . 16 table 5. functionalities depending on the working mode (from run/active down to standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 6. stm32l0xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 7. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 8. internal voltage reference measured values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 9. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 10. comparison of i2c analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 11. stm32l051x6/8 i 2 c implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 12. usart implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 13. spi/i2s implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 14. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 15. stm32l051x6/8 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 16. alternate function port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 17. alternate function port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 18. alternate function port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 19. alternate function port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 20. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 21. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 22. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 23. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 24. embedded reset and power control block characterist ics. . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 25. embedded internal reference voltage calibration valu es . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 26. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 table 27. current consumption in run mode, code with data processing running from flash. . . . . . 55 table 28. current consumption in run mode vs code type, code with data processing running from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 29. current consumption in run mode, code wit h data processing running from ram . . . . . . 57 table 30. current consumption in run mode vs code type, code with data processing running from ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 31. current consumption in sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 32. current consumption in low-power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 33. current consumption in low-power sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 34. typical and maximum current consumptions in st op mode . . . . . . . . . . . . . . . . . . . . . . . . 61 table 35. typical and maximum current consumptions in standby mode . . . . . . . . . . . . . . . . . . . . . 62 table 36. average current consumption during wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 37. peripheral current consumption in run or sleep mo de . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 38. peripheral current consumption in stop and stan dby mode . . . . . . . . . . . . . . . . . . . . . . . 64 table 39. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 40. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 41. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 42. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 43. lse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 44. 16 mhz hsi16 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 0 table 45. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 list of tables stm32l051x6 stm32l051x8 6/119 docid025938 rev 4 table 46. msi oscillator ch aracteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 47. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 48. ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 49. flash memory and dat a eeprom characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 50. flash memory and data eeprom endurance and retention . . . . . . . . . . . . . . . . . . . . . . . 74 table 51. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 52. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 53. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 54. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 55. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 56. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 57. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 58. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 59. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 60. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 61. r ain max for f adc = 14 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 62. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 63. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 table 64. temperature sensor characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 65. comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 66. comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 67. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 68. i2c analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 69. spi characteristics in voltage range 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 70. spi characteristics in voltage range 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 71. spi characteristics in voltage range 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 72. i2s characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 73. lqfp32, 7 x 7 mm, 32-pin low-profile quad flat package mechanical data . . . . . . . . . . . . 99 table 74. ufqfpn32, 5 x 5 mm, 32-pin package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . 102 table 75. lqfp48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . 105 table 76. lqfp64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data. . . . . . . . . . 108 table 77. wlcsp36 0.4 mm pitch wafer-level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 78. tfbga64, 5 x 5 mm, 64-bump thin profile fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 79. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 80. stm32l051x6/8 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 81. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 docid025938 rev 4 7/119 stm32l051x6 stm32l051x8 list of figures 8 list of figures figure 1. stm32l051x6/8 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 2. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 3. stm32l051x6/8 wlcsp36 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 4. stm32l051x6/8 lqfp32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 5. stm32l051x6/8 ufqfpn32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 6. stm32l051x6/8 lqfp48 pinout - 7 x 7 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 7. stm32l051x6/8 lqfp64 pinout - 10 x 10 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 8. stm32l051x6/8 tfbga64 ballout - 5x 5 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 9. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 10. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 11. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 12. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 13. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 14. idd vs vdd, at ta= 25/55/85 /105 c, run mode, code running from flash memory, range 2, hse, 1ws . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 15. idd vs vdd, at ta= 25/55/85 /105 c, run mode, code running from flash memory, range 2, hsi16, 1ws . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 16. idd vs vdd, at ta= 25/55/ 85/105/125 c, low-power run mode, code running from ram, range 3, msi (range 0) at 64 khz, 0 ws . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 17. idd vs vdd, at ta= 25/55/ 85 /105/125 c, stop mode with rtc enabled and running on lse low drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 18. idd vs vdd, at ta= 25/55/85/ 105/125 c, stop mode with rtc disabled, all clocks off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 19. high-speed external clock source ac timing diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 20. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 21. hse oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 22. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 23. hsi16 minimum and maximum value versus temperat ure . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 24. vih/vil versus vdd (cmos i/os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 9 figure 25. vih/vil versus vdd (ttl i/os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 26. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 27. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 28. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 29. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 30. power supply and reference decoupling (v ref+ not connected to v dda ). . . . . . . . . . . . . . 87 figure 31. power supply and reference decoupling (v ref+ connected to v dda ). . . . . . . . . . . . . . . . . 87 figure 32. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 33. spi timing diagram - slave mode and cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 34. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 35. i 2 s slave timing diagram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 36. i 2 s master timing diag ram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 37. lqfp32, 7 x 7 mm, 32-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . 98 figure 38. lqfp32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 39. lqfp32 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 40. ufqfpn32, 5 x 5 mm, 32-pin package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 41. ufqfpn32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 42. ufqfpn32 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 43. lqfp48, 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 104 list of figures stm32l051x6 stm32l051x8 8/119 docid025938 rev 4 figure 44. lqfp48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 figure 45. lqfp48 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 46. lqfp64, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 107 figure 47. lqfp64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8 figure 48. lqfp64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 49. wlcsp36 0.4 mm pitch wafer-level chip scale package outline . . . . . . . . . . . . . . . . . . . 110 figure 50. tfbga64, 5 x 5 mm, 64-bump thin profile fine pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 51. tfbga64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 52. thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 docid025938 rev 4 9/119 stm32l051x6 stm32l051x8 introduction 32 1 introduction the ultra-low-power stm32l051x6/8 are offered in 6 different package types: from 48 pins to 64 pins. depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. these features make the ultra-low-power st m32l051x6/8 microcontrollers suitable for a wide range of applications: ? gas/water meters and industrial sensors ? healthcare and fitness equipment ? remote control and user interface ? pc peripherals, gaming, gps equipment ? alarm system, wired and wireless sensors, video intercom this stm32l051x6/8 datasheet should be re ad in conjunction with the stm32l0x1xx reference manual (rm0377) . for information on the arm ? cortex ? -m0+ core please refer to the cortex ? -m0+ technical reference manual, available from the www.arm.com website. figure 1 shows the general block diagram of the device family. description stm32l051x6 stm32l051x8 10/119 docid025938 rev 4 2 description the access line ultra-low-power stm32l051x6/8 microcontrollers incorporate the high- performance arm ? cortex ? -m0+ 32-bit risc core operating at a 32 mhz frequency, a memory protection unit (mpu), high-speed embedded memories ( 64 kbytes of flash program memory, 2 kbytes of data eeprom and 8 kbytes of ram) plus an extensive range of enhanced i/os and peripherals. the stm32l051x6/8 devices provide high power efficiency for a wide range of performance. it is achieved with a large choice of internal and external clock sources, an internal voltage adaptation and several low-power modes. the stm32l051x6/8 devices offer several analog features, one 12-bit adc with hardware oversampling, two ultra-low-power comparators, several timers, one low-power timer (lptim), three general-purpose 16-bit timers and one basic timer, one rtc and one systick which can be used as timebases. they also feature two watchdogs, one watchdog with independent clock and window capability and one window watchdog based on bus clock. moreover, the stm32l051x6/8 devices em bed standard and advanced communication interfaces: up to two i2cs, two spis, one i2 s, two usarts, a low-power uart (lpuart), . the stm32l051x6/8 also include a real-time clock and a set of backup registers that remain powered in standby mode. the ultra-low-power stm32l051x6/8 devices operate from a 1.8 to 3.6 v power supply (down to 1.65 v at power down) with bor and from a 1.65 to 3.6 v power supply without bor option. they are available in the -40 to +125 c temperature range. a comprehensive set of power-saving modes allows the design of low-power applications. docid025938 rev 4 11/119 stm32l051x6 stm32l051x8 description 32 2.1 device overview table 2. ultra-low-power stm32l051x6/x8 device features and peripheral counts peripheral stm32 l051k6 stm32 l051t6 stm32 l051c6 stm32 l051r6 stm32 l051k8 stm32 l051t8 stm32 l051c8 stm32 l051r8 flash (kbytes) 32 64 data eeprom (kbytes) 22 ram (kbytes) 88 timers general- purpose 33 basic 11 lptimer 11 rtc/systick/iwdg/wwdg 1/1/1/1 1/1/1/1 communicati on interfaces spi/(i2s) 1/(0) 1/(0) 2/(1) 2/(1) 1/(0) 1/(1) 2/(1) 2/(1) i 2 c 1222 1222 usart 22 lpuart 0111 0111 gpios 27 (1) 29 37 51 (2) 27 (1) 29 37 51 (2) clocks: hse/lse/hsi/msi/lsi 0/1/1/1/1 1/1/1/1/ 1 1/1/1/1/1 1/1/1/1/1 0/1/1/1/1 1/1/1/1/ 1 1/1/1/1/1 1/1/1/1/1 12-bit synchronized adc number of channels 1 10 1 10 1 10 1 16 (2) 1 10 1 10 1 10 1 16 (2) comparators 22 max. cpu frequency 32 mhz operating voltage 1.8 v to 3.6 v (down to 1.65 v at power-down) with bor option 1.65 v to 3.6 v without bor option operating temperatures ambient temperature: ?40 to +125 c junction temperature: ?40 to +130 c packages lqfp32, ufqfpn 32 wlcs p36 lqfp48 lqfp64 tfbga 64 lqfp32, ufqfpn 32 wlcs p36 lqfp48 lqfp64 tfbga 64 1. lqfp32 has two gpios, less than ufqfpn32 (27). 2. tfbga64 has one gpio, one adc input and one c apacitive sensing channel less than lqfp64. description stm32l051x6 stm32l051x8 12/119 docid025938 rev 4 figure 1. stm32l051x6/8 block diagram & 2 5 7 ( ; 0 & 3 8 ) p d [ 0 + ] 6 : ' 0 3 8 1 9 , & * 3 , 2 3 2 5 7 $ * 3 , 2 3 2 5 7 % * 3 , 2 3 2 5 7 & * 3 , 2 3 2 5 7 ' * 3 , 2 3 2 5 7 + 7 h p s v h q v r u 5 ( 6 ( 7 & / . ) / $ 6 + ( ( 3 5 2 0 % 2 2 7 5 $ 0 ' 0 $ $ + % ) p d [ 0 + ] & 5 & % 5 , ' * ( $ 3 % ) , 5 ( : $ / / ' % * ( ; 7 , $ ' & 6 3 , 8 6 $ 5 7 7 , 0 & 2 0 3 / 6 ( 7 , 0 % 5 , ' * ( $ 3 % 7 , 0 , & , & 8 6 $ 5 7 / 3 8 $ 5 7 6 3 , , 6 7 , 0 , : ' * 5 7 & : : ' * / 3 7 , 0 % & . 3 5 ( * + 6 ( + 6 , 0 3 / / 0 6 , / 6 , 3 0 8 5 ( * 8 / $ 7 2 5 9 ' ' 9 ' ' $ 9 5 ( ) b 2 8 7 1 5 6 7 3 9 ' b , 1 2 6 & b , 1 2 6 & b 2 8 7 2 6 & b , 1 2 6 & b 2 8 7 : . 8 3 [ 3 $ > @ 3 + > @ 3 ' > @ 3 & > @ 3 % > @ $ , 1 [ 0 , 6 2 0 2 6 , 6 & . 1 6 6 5 ; 7 ; 5 7 6 & 7 6 & . f k f k , 1 3 , 1 0 2 8 7 , 1 , 1 ( 7 5 2 8 7 6 & / 6 ' $ 6 0 % $ 6 & / 6 ' $ 6 0 % $ 5 ; 7 ; 5 7 6 & 7 6 & . 5 ; 7 ; 5 7 6 & 7 6 0 , 6 2 0 & . 0 2 6 , 6 ' 6 & . & . 1 6 6 : 6 f k 6 : ' 0 6 9 & 2 0 3 , 1 3 , 1 0 2 8 7 docid025938 rev 4 13/119 stm32l051x6 stm32l051x8 description 32 2.2 ultra-low-power device continuum the ultra-low-power family offers a large choice of core and features, from proprietary 8-bit core to up arm ? cortex ? -m3, including arm ? cortex ? -m0+. the stm32lx series are the best choice to answer your needs in terms of ultra-low-power features. the stm32 ultra- low-power series are the best solution for applications such as gaz/water meter, keyboard/mouse or fit ness and healthcare application. several built-in features like lcd drivers, dual-bank memory, low-power run mode , operational amplifiers, aes 128-bit, dac, crystal-less usb and many other definitely help you building a highly cost optimized application by reducing bom cost. stmicroelectronics, as a reliable and long-term manufacturer, ensures as much as possible pin-to-pin compatibility between all stm8lx and stm32lx on one hand, and between all stm32lx and stm32fx on the other hand. thanks to this unpr ecedented scalability, your legacy application can be upgraded to respond to the latest market feature and efficiency requirements. functional overview stm32l051x6 stm32l051x8 14/119 docid025938 rev 4 3 functional overview 3.1 low-power modes the ultra-low-power stm32l051x6/8 support dyna mic voltage scaling to optimize its power consumption in run mode. the voltage from the internal low-drop regulator that supplies the logic can be adjusted according to the system?s maximum operating frequency and the external voltage supply. there are three power consumption ranges: ? range 1 (v dd range limited to 1.71-3.6 v), with the cpu running at up to 32 mhz ? range 2 (full v dd range), with a maximum cpu frequency of 16 mhz ? range 3 (full v dd range), with a maximum cpu frequency limited to 4.2 mhz seven low-power modes are provided to achieve the best compromise between low-power consumption, short startup time and available wakeup sources: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. sleep mode power consumption at 16 mhz is about 1 ma with all peripherals off. ? low-power run mode this mode is achieved with t he multispeed in ternal (msi) rc oscilla tor set to the low- speed clock (max 131 khz), execution from sram or flash memory, and internal regulator in low-power mode to minimize the regulator's operating current. in low- power run mode, the clock frequency and the number of enabled peripherals are both limited. ? low-power sleep mode this mode is achieved by entering sleep mode with the internal voltage regulator in low-power mode to minimize the regulator?s operating current. in low-power sleep mode, both the clock frequency and the number of enabled peripherals are limited; a typical example would be to have a timer running at 32 khz. when wakeup is triggered by an event or an interrupt, the system reverts to the run mode with the regulator on. ? stop mode with rtc the stop mode achieves the lowest powe r consumption while retaining the ram and register contents and real time clock. all clocks in the v core domain are stopped, the pll, msi rc, hse crystal and hsi rc oscillato rs are disabled. the lse or lsi is still running. the voltage regulator is in the low-power mode. some peripherals featuring wakeup capability can enable the hsi rc during stop mode to detect their wakeup condition. the device can be woken up from stop mode by any of the exti line, in 3.5 s, the processor can serve the interrupt or resume the code. the exti line source can be any gpio. it can be the pvd output, the comp arator 1 event or comparator 2 event docid025938 rev 4 15/119 stm32l051x6 stm32l051x8 functional overview 32 (if internal reference voltage is on), it c an be the rtc alarm/tamper/timestamp/wakeup events, the usart/i2c/lpuart/lptimer wakeup events. ? stop mode without rtc the stop mode achieves the lowest powe r consumption while retaining the ram and register contents. all clocks are stopped, the pll, msi rc, hsi and lsi rc, hse and lse crystal oscillato rs are disabled. some peripherals featuring wakeup capability can enable the hsi rc during stop mode to detect their wakeup condition. the voltage regulator is in the low-power mode. the device can be woken up from stop mode by any of the exti line, in 3.5 s, the processor can serve the interrupt or resume the code. the exti line source can be any gpio. it can be the pvd output, the comparator 1 event or comparator 2 event (if internal reference voltage is on). it can also be wakened by the usart/i2 c/lpuart/lptimer wakeup events. ? standby mode with rtc the standby mode is used to achieve the lowest power consumption and real time clock. the internal voltage regulator is switched off so that the entire v core domain is powered off. the pll, msi rc, hse crystal and hsi rc oscillators are also switched off. the lse or lsi is still running. after entering standby mode, the ram and register contents are lost except fo r registers in the standby circuitry (wakeup logic, iwdg, rtc, lsi, lse crystal 32 khz oscillator, rcc_csr register). the device exits standby mode in 60 s when an external reset (nrst pin), an iwdg reset, a rising edge on one of the three wkup pins, rtc alarm (alarm a or alarm b), rtc tamper event, rtc timestamp event or rtc wakeup event occurs. ? standby mode without rtc the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire v core domain is powered off. the pll, msi rc, hsi and lsi rc, hse and lse cr ystal oscillators are also switched off. after entering standby mode, the ram and register contents are lost except for registers in the standby circuitry (wakeup logic, iwdg, rtc, lsi, lse crystal 32 khz oscillator, rcc_csr register). the device exits standby mode in 60 s when an external reset (nrst pin) or a rising edge on one of the three wkup pin occurs. note: the rtc, the iwdg, and the corresponding clock sources are not stopped automatically by entering stop or standby mode. functional overview stm32l051x6 stm32l051x8 16/119 docid025938 rev 4 table 3. functionalities depending on the operating power supply range operating power supply range functionalities depending on the operating power supply range adc operation dynamic voltage scaling range i/o operation v dd = 1.65 to 1.71 v adc only, conversion time up to 570 msps range 2 or range 3 degraded speed performance v dd = 1.71 to 1.8 v (1) 1. cpu frequency changes from initial to final must respec t "fcpu initial <4*fcpu final". it must also respect 5 s delay between two changes. for example to switch fr om 4.2 mhz to 32 mhz, you can switch from 4.2 mhz to 16 mhz, wait 5 s, then switch from 16 mhz to 32 mhz. adc only, conversion time up to 1.14 msps range 1, range 2 or range 3 degraded speed performance v dd = 1.8 to 2.0 v (1) conversion time up to 1.14 msps range1, range 2 or range 3 degraded speed performance v dd = 2.0 to 2.4 v conversion time up to 1.14 msps range 1, range 2 or range 3 full speed operation v dd = 2.4 to 3.6 v conversion time up to 1.14 msps range 1, range 2 or range 3 full speed operation table 4. cpu frequency range depending on dynamic voltage scaling cpu frequency range dynamic voltage scaling range 16 mhz to 32 mhz (1ws) 32 khz to 16 mhz (0ws) range 1 8 mhz to 16 mhz (1ws) 32 khz to 8 mhz (0ws) range 2 32 khz to 4.2 mhz (0ws) range 3 table 5. functionalities depending on the working mode (from run/active down to standby) (1) ips run/active sleep low- power run low- power sleep stop standby wakeup capability wakeup capability cpu y -- y -- -- -- flash memory o o o o -- -- ram y y y y y -- backup registers y y y y y y docid025938 rev 4 17/119 stm32l051x6 stm32l051x8 functional overview 32 eeprom o o o o -- -- brown-out reset (bor) oooooooo dma o o o o -- -- programmable voltage detector (pvd) oooooo- power-on/down reset (por/pdr) yyyyyyyy high speed internal (hsi) oo---- (2) -- high speed external (hse) oooo-- -- low speed internal (lsi) ooooo o low speed external (lse) ooooo o multi-speed internal (msi) ooyy-- -- inter-connect controller yyyyy -- rtc o o o o o o o rtc tamper o o o o o o o o auto wakeup (awu) oooooooo usart o o o o o (3) o-- lpuart o o o o o (3) o-- spi o o o o -- -- i2c o o o o o (4) o-- adc o o o o -- -- temperature sensor ooooo -- comparators o o o o o o -- 16-bit timers o o o o -- -- lptimer o o o o o o iwdg o o o o o o o o table 5. functionalities depending on the working mode (from run/active down to standby) (continued) (1) ips run/active sleep low- power run low- power sleep stop standby wakeup capability wakeup capability functional overview stm32l051x6 stm32l051x8 18/119 docid025938 rev 4 3.2 interconnect matrix several peripherals are directly interconnec ted. this allows autonomous communication between peripherals, thus saving cpu resources and power consumption. in addition, these hardware connections allow fast and predictable latency. depending on peripherals, these interconnect ions can operate in run, sleep, low-power run, low-power sleep and stop modes. wwdg o o o o -- -- systick timer o o o o -- gpios o o o o o o 2 pins wakeup time to run mode 0 s 0.36 s 3 s 32 s 3.5 s 50 s consumption v dd =1.8 to 3.6 v (typ) down to 140 a/mhz (from flash) down to 37 a/mhz (from flash) down to 8 a down to 4.5 a 0.4 a (no rtc) v dd =1.8 v 0.28 a (no rtc) v dd =1.8 v 0.8 a (with rtc) v dd =1.8 v 0.65 a (with rtc) v dd =1.8 v 0.4 a (no rtc) v dd =3.0 v 0.29 a (no rtc) v dd =3.0 v 1 a (with rtc) v dd =3.0 v 0.85 a (with rtc) v dd =3.0 v 1. legend: ?y? = yes (enable). ?o? = optional can be enabled/disabled by software) ?-? = not available 2. some peripherals with wakeup from stop capability can reques t hsi to be enabled. in this case, hsi is woken up by the peripheral, and only feeds the peripheral which requested it. hsi is automatically put off when the peripheral does not need it anymore. 3. uart and lpuart reception is functional in stop mode. it generates a wakeup interrupt on start.to generate a wakeup on address match or received frame event, the lpuart can run on lse clock while the uart has to wake up or keep running the hsi clock. 4. i2c address detection is functional in stop mode. it generates a wakeup interrupt in case of address match. it will wake up the hsi during recepti on. table 5. functionalities depending on the working mode (from run/active down to standby) (continued) (1) ips run/active sleep low- power run low- power sleep stop standby wakeup capability wakeup capability docid025938 rev 4 19/119 stm32l051x6 stm32l051x8 functional overview 32 3.3 arm ? cortex ? -m0+ core with mpu the cortex-m0+ processor is an entry-level 32-bit arm cortex processor designed for a broad range of embedded applications. it offers significant benefits to developers, including: ? a simple architecture that is easy to learn and program ? ultra-low power, energy-efficient operation ? excellent code density ? deterministic, high-performance interrupt handling ? upward compatibility with co rtex-m processor family ? platform security robustness, with in tegrated memory protection unit (mpu). the cortex-m0+ processor is built on a highly area and power optimized 32-bit processor core, with a 2-stage pipeline von neumann architecture. the processor delivers exceptional energy efficiency through a small but powerful instruction set and extensively optimized design, providing high-end processing hardware including a single-cycle multiplier. the cortex-m0+ processor provides the except ional performance expected of a modern 32- bit architecture, with a higher code density t han other 8-bit and 16-bit microcontrollers. table 6. stm32l0xx peripherals interconnect matrix interconnect source interconnect destination interconnect action run sleep low- power run low- power sleep stop compx tim2,tim21, tim22 timer input channel, trigger from analog signals comparison yy y y - lptim timer input channel, trigger from analog signals comparison yy y y y timx timx timer triggered by other timer yy y y - rtc tim21 timer triggered by auto wake-up yy y y - lptim timer triggered by rtc event yy y y y all clock source timx clock source used as input channel for rc measurement and trimming yy y y - gpio timx timer input channel and trigger yy y y - lptim timer input channel and trigger yy y y y adc conversion trigger y y y y - functional overview stm32l051x6 stm32l051x8 20/119 docid025938 rev 4 owing to its embedded arm core, the stm32l051x6/8 are compatible with all arm tools and software. nested vectored interrupt controller (nvic) the ultra-low-power stm32l051x6/8 embed a nest ed vectored interrupt controller able to handle up to 32 maskable interrupt channels and 4 priority levels. the cortex-m0+ processor closely integrates a configurable nested vectored interrupt controller (nvic), to deliver industry-leading interrupt performance. the nvic: ? includes a non-mask able interrupt (nmi) ? provides zero jitte r interrupt option ? provides four interr upt priority levels the tight integration of the processor core and nvic provides fast execution of interrupt service routines (isrs), dramatically reducing the interrupt latency. this is achieved through the hardware stacking of registers, and the abilit y to abandon and restart load- multiple and store-multiple operations. interrupt handlers do not require any assembler wrapper code, removing any code overhead from the isrs. tail-chaining optimization also significantly reduces the overhead when switching from one isr to another. to optimize low-power designs, the nvic int egrates with the sleep modes, that include a deep sleep function that enables the entire device to enter rapidly stop or standby mode. this hardware block provides flexible interrupt management features with minimal interrupt latency. 3.4 reset and supply management 3.4.1 power supply schemes ? v dd = 1.65 to 3.6 v: external power supply fo r i/os and the internal regulator. provided externally through v dd pins. ? v ssa , v dda = 1.65 to 3.6 v: external analog power supplies for adc reset blocks, rcs and pll. v dda and v ssa must be connected to v dd and v ss , respectively. 3.4.2 power supply supervisor the deviceshave an integrated zeropower power-on reset (por)/power-down reset (pdr) that can be coupled with a brownout reset (bor) circuitry. two versions are available: ? the version with bor activated at power-on operates between 1.8 v and 3.6 v. ? the other version without bor oper ates between 1.65 v and 3.6 v. after the v dd threshold is reached (1.65 v or 1.8 v depending on the bor which is active or not at power-on), the option byte loading process starts, either to confirm or modify default thresholds, or to disable the bor permanently: in this case, the vdd min value becomes 1.65 v (whatever the version, bo r active or not, at power-on). when bor is active at power- on, it ensures proper operation starting from 1.8 v whatever the power ramp-up phase before it reaches 1.8 v. when bor is not active at power-up, the power ramp-up should guarantee that 1.65 v is reached on v dd at least 1 ms after it exits the por area. docid025938 rev 4 21/119 stm32l051x6 stm32l051x8 functional overview 32 five bor thresholds are available through opti on bytes, starting from 1.8 v to 3 v. to reduce the power consumption in stop mode, it is possible to automatically switch off the internal reference voltage (v refint ) in stop mode. the device remains in reset mode when v dd is below a specified threshold, v por/pdr or v bor , without the need for any external reset circuit. note: the start-up time at power-on is typically 3.3 ms when bor is active at power-up, the start- up time at power-on can be decreased down to 1 ms typically for devices with bor inactive at power-up. the devices feature an embedded programmable voltage detector (pvd) that monitors the v dd/vdda power supply and compares it to the v pvd threshold. this pvd offers 7 different levels between 1.85 v and 3.05 v, chosen by software, with a step around 200 mv. an interrupt can be generated when v dd/vdda drops below the v pvd threshold and/or when v dd/vdda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. 3.4.3 voltage regulator the regulator has three operation modes: main (mr), low power (lpr) and power down. ? mr is used in run mode (nominal regulation) ? lpr is used in the low-power run, low-power sleep and stop modes ? power down is used in standby mode. the regulator output is high impedance, the kernel circuitry is powered down, inducing zero consumption but the contents of the registers and ram are lost except for the st andby circuitry (wakeup logic, iwdg, rtc, lsi, lse crystal 32 khz oscillator, rcc_csr). 3.4.4 boot modes at startup, boot0 pin and boot1 option bit are used to select one of three boot options: ? boot from flash memory ? boot from system memory ? boot from embedded ram the boot loader is located in system memory. it is used to reprogram the flash memory by using usart1(pa9, pa10), spi 1(pa4, pa5, pa6, pa7) or spi2 (pb12, pb13, pb14, pb15) and usart2(pa2, pa3). see stm32? micr ocontroller system memory boot mode an2606 for details. functional overview stm32l051x6 stm32l051x8 22/119 docid025938 rev 4 3.5 clock management the clock controller distributes the clocks coming from different oscillators to the core and the peripherals. it also manages clock gating for low-power modes and ensures clock robustness. it features: ? clock prescaler to get the best trade-off between speed a nd current consumption, the clock frequency to the cpu and peripherals can be adjusted by a programmable prescaler. ? safe clock switching clock sources can be changed safely on the fly in run mode through a configuration register. ? clock management to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. ? system clock source three different clock sources can be used to drive the master clock sysclk: ? 1-24 mhz high-speed external crystal (hse), that can supply a pll ? 16 mhz high-speed internal rc oscillator (h si), trimmable by software, that can supply a pll ? multispeed internal rc oscilla tor (msi), trimmable by soft ware, able to generate 7 frequencies (65 khz, 131 khz, 262 khz, 524 khz, 1.05 mhz, 2.1 mhz, 4.2 mhz). when a 32.768 khz clock source is available in the system (lse), the msi frequency can be trimmed by software down to a 0.5% accuracy. ? auxiliary clock source two ultra-low-power clock sources that c an be used to drive the real-time clock: ? 32.768 khz low-speed external crystal (lse) ? 37 khz low-speed internal rc (lsi), also used to drive the independent watchdog. the lsi clock can be measured using the high-speed internal rc oscillator for greater precision. ? rtc clock source the lsi, lse or hse sources can be chosen to clock the rtc, whatever the system clock. ? startup clock after reset, the microcontroller restarts by default with an internal 2 mhz clock (msi). the prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. ? clock security system (css) this feature can be enabled by software. if an hse clock failure occurs, the master clock is automatically switched to hsi and a software interrupt is generated if enabled. another clock security system can be enabled, in case of failure of the lse it provides an interrupt or wakeup event which is generated if enabled. ? clock-out capability (mco: microcontroller clock output) it outputs one of the internal clocks for external use by the application. several prescalers allow the configuration of the ahb fr equency, each apb (apb1 and apb2) domains. the maximum frequency of the ahb and the apb domains is 32 mhz. see figure 2 for details on the clock tree. docid025938 rev 4 23/119 stm32l051x6 stm32l051x8 functional overview 32 figure 2. clock tree 0 6 y 9 / h j h q g + 6 ( + l j k v s h h g h [ w h u q d o f o r f n v l j q d o + 6 , + l j k v s h h g l q w h u q d o f o r f n v l j q d o / 6 , / r z v s h h g l q w h u q d o f o r f n v l j q d o / 6 ( / r z v s h h g h [ w h u q d o f o r f n v l j q d o 0 6 , 0 x o w l v s h h g l q w h u q d o f o r f n v l j q d o : d w f k g r j / 6 / 6 , 5 & / 6 ( 2 6 & 5 7 & / 6 , w h p s r # 9 + 6 , 5 & / h y h o v k l i w h u v + 6 ( 2 6 & / h y h o v k l i w h u v / 6 8 0 + ] & o r f n ' h w h f w r u / 6 ' / 6 ( w h p s r 0 6 , 5 & / h y h o v k l i w h u v / h y h o v k l i w h u v 3 / / ; $ + % 3 5 ( 6 & ? & o r f n 6 r x u f h & r q w u r o # 9 # 9 # 9 # 9 # 9 # 9 # 9 # 9 , & & / . / 3 8 $ 5 7 8 $ 5 7 & / . / 3 7 , 0 & / . / 6 ( + 6 , 6 < 6 & / . 3 & / . / 6 , q r w v o h h s r u g h h s v o h h s q r w v o h h s r u g h h s v o h h s q r w g h h s v o h h s q r w g h h s v o h h s + & / . 7 , 0 [ & / . & . b 3 : 5 ) & / . 3 / / & / . + 6 ( + 6 , 0 6 , / 6 ( / 6 , + 6 ( s u h v h q w r u q r w # 9 # 9 ' ' & 2 5 ( f n b u f k v + 6 , 0 6 , 0 + ] f n b s o o l q ( q d e o h : d w f k g r j 5 7 & h q d e o h $ ' & h q d e o h $ ' & & / . / 6 8 / 6 ' / 6 ' 0 & 2 0 & 2 6 ( / 3 / / 6 5 & 5 7 & 6 ( / 6 \ v w h p & o r f n 3 h u l s k h u d o v h q d e o h 3 h u l s k h u d o v h q d e o h 3 h u l s k h u d o f o r f n h q d e o h 3 & / . w r $ 3 % s h u l s k h u d o v , i $ 3 % s u h v f [ h o v h [ w r 7 , 0 [ 3 h u l s k h u d o f o r f n h q d e o h $ 3 % 3 5 ( 6 & 3 h u l s k h u d o f o r f n h q d e o h 3 & / . w r $ 3 % s h u l s k h u d o v 0 + ] p d [ , i $ 3 % s u h v f [ h o v h [ w r 7 , 0 [ 3 h u l s k h u d o v h q d e o h $ 3 % 3 5 ( 6 & functional overview stm32l051x6 stm32l051x8 24/119 docid025938 rev 4 3.6 low-power real-time cl ock and backup registers the real time clock (rtc) and the 5 backup registers are supplied in all modes including standby mode. the backup registers are five 32-b it registers used to store 20 bytes of user application data. they are not reset by a system reset, or when the device wakes up from standby mode. the rtc is an independent bcd timer/counter. its main features are the following: ? calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in bcd (binary-coded decimal) format ? automatically correction for 28, 29 (leap year), 30, and 31 day of the month ? two programmable alarms with wake up from stop and stan dby mode capability ? periodic wakeup from stop and standby with programmable resolution and period ? on-the-fly correction from 1 to 32767 rtc clock pulses. this can be used to synchronize it with a master clock. ? reference clock detection: a more precise se cond source clock (50 or 60 hz) can be used to enhance the calendar precision. ? digital calibration circuit with 1 ppm resolu tion, to compensate for quartz crystal inaccuracy ? 2 anti-tamper detection pins with programma ble filter. the mcu can be woken up from stop and standby modes on tamper event detection. ? timestamp feature which can be used to save the calendar content. this function can be triggered by an event on the timestamp pin, or by a tamper event. the mcu can be woken up from stop and standby modes on timestamp event detection. the rtc clock sources can be: ? a 32.768 khz external crystal ? a resonator or oscillator ? the internal low-power rc oscillator (typical frequency of 37 khz) ? the high-speed external clock 3.7 general-purpose inputs/outputs (gpios) each of the gpio pins can be configured by so ftware as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions, and can be individually remapped using dedicated alternate function regi sters. all gpios are high current capable. each gpio output, speed can be slowed (40 mh z, 10 mhz, 2 mhz, 400 khz). the alternate function configuration of i/os can be locked if needed following a specific sequence in order to avoid spurious writing to the i/o registers. the i/o controller is connected to a dedicated io bus with a toggling speed of up to 32 mhz. extended interrupt/event controller (exti) the extended interrupt/event co ntroller consists of 28 edge det ector lines used to generate interrupt/event requests. each line can be individually configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the in ternal apb2 clock period. up to 51 gpios can be connected to the 16 configurable interr upt/event lines. the 12 other lines are connected to pvd, rtc, usarts, lpuart, lptimer or comparator events. docid025938 rev 4 25/119 stm32l051x6 stm32l051x8 functional overview 32 3.8 memories the stm32l051x6/8 deviceshave the following features: ? 8 kbytes of embedded sram accessed (read/ write) at cpu clock speed with 0 wait states. with the enhanced bus matrix, op erating the ram does not lead to any performance penalty during accesses to th e system bus (ahb and apb buses). ? the non-volatile memory is divided into three arrays: ? 32 or 64 kbytes of embedded flash program memory ? 2 kbytes of data eeprom ? information block containing 32 user and factory options bytes plus 4 kbytes of system memory the user options bytes are used to write-pr otect or read-out protect the memory (with 4 kbyte granularity) and/or readout-protect the whole memory with the following options: ? level 0 : no protection ? level 1 : memory readout protected. the flash memory cannot be read from or written to if either debug features are connected or boot in ram is selected ? level 2 : chip readout protected, debug features (cortex-m0+ serial wire) and boot in ram selection disabled (debugline fuse) the firewall protects parts of code/data from acce ss by the rest of the code that is executed outside of the protected area. the granularit y of the protected code segment or the non- volatile data segment is 256 by tes (flash or eeprom) against 64 bytes for the volatile data segment (ram). the whole non-volatile memory embeds th e error correction code (ecc) feature. 3.9 direct memory access (dma) the flexible 7-channel, general-purpose dma is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. the dma controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer. each channel is connected to dedicated hardware dma requests, with software trigger support for each channel. configuration is done by software and transfer sizes between source and destination are independent. the dma can be used with the main peripherals: spi, i 2 c, usart, lpuart, general-purpose timers, and adc. 3.10 analog-to-digita l converter (adc) a native 12-bit, extended to 16-bit through hardware oversampling, analog-to-digital converter is embedded into stm32l051x6/8 device. it has up to 16 external channels and 3 internal channels (temperature sensor, voltage reference). it performs conversions in single- shot or scan mode. in scan mode, automatic conversion is performed on a selected group of analog inputs. functional overview stm32l051x6 stm32l051x8 26/119 docid025938 rev 4 the adc frequency is independent from t he cpu frequency, allo wing maximum sampling rate of 1.14 msps even with a low cpu spee d. the adc consumption is low at all frequencies (~25 a at 10 ksps, ~200 a at 1msps). an auto-shutdown function guarantees that the adc is powered off ex cept during the active conversion phase. the adc can be served by the dma controller. it can operate from a supply voltage down to 1.65 v. the adc features a hardware oversampler up to 256 samples, this improves the resolution to 16 bits (see an2668). an analog watchdog feature allows very precis e monitoring of the converted voltage of one, some or all scanned channels. an interrupt is generated when the converted voltage is outside the programmed thresholds. the events generated by the general-purpose timers (timx) can be internally connected to the adc start triggers, to allow the application to synchronize a/d conversions and timers. 3.11 temperature sensor the temperature sensor (t sense ) generates a voltage v sense that varies linearly with temperature. the temperature sensor is internally connec ted to the adc_in18 input channel which is used to convert the sensor output voltage into a digital value. the sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. as the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. to improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by st. the te mperature sensor factory calibration data are stored by st in the system memory area, accessible in read-only mode. 3.11.1 internal voltage reference (v refint ) the internal voltage reference (v refint ) provides a stable (bandgap) voltage output for the adc and comparators. v refint is internally con nected to the adc_in17 input channel. it enables accurate monitoring of the v dd value (when no external voltage, v ref+ , is available for adc). the precise voltage of v refint is individually measured for each part by st during production test and stored in the system memo ry area. it is accessible in read-only mode. table 7. temperature sensor calibration values calibration value name description memory address tsense_cal1 ts adc raw data acquired at temperature of 30 c, v dda = 3 v 0x1ff8 007a - 0x1ff8 007b tsense_cal2 ts adc raw data acquired at temperature of 130 c v dda = 3 v 0x1ff8 007e - 0x1ff8 007f docid025938 rev 4 27/119 stm32l051x6 stm32l051x8 functional overview 32 3.12 ultra-low-power comparators and reference voltage the stm32l051x6/8 embed two comparators sharing the same current bias and reference voltage. the reference voltage can be internal or external (coming from an i/o). ? one comparator with ultra low consumption ? one comparator with rail-to-rail inputs, fast or slow mode. ? the threshold can be one of the following: ? external i/o pins ? internal reference voltage (v refint ) ? submultiple of internal reference voltage(1/4, 1/2, 3/4) for the rail to rail comparator. both comparators can wake up the devices from stop mode, and be combined into a window comparator. the internal reference voltage is available externally via a low-power / low-current output buffer (driving current capability of 1 a typical). 3.13 system config uration controller the system configuration cont roller provides the capabilit y to remap some alternate functions on different i/o ports. the highly flexible routing inte rface allows the application firm ware to control the routing of different i/os to the tim2, tim21, tim22 and lp tim timer input captures . it also controls the routing of internal analog signals to adc, comp1 and comp2 and the internal reference voltage v refint . table 8. internal voltage reference measured values calibration value name description memory address vrefint_cal raw data acquired at temperature of 30 c v dda = 3 v 0x1ff8 0078 - 0x1ff8 0079 functional overview stm32l051x6 stm32l051x8 28/119 docid025938 rev 4 3.14 timers and watchdogs the ultra-low-power stm32l051x6/8 devices include three general-purpose timers, one low- power timer (lptm), one basic timer, two watchdog timers and the systick timer. table 9 compares the features of the general-purpose and basic timers. 3.14.1 general-purpose timers (tim2, tim21 and tim22) there are three synchronizable general-purpose timers embedded in the stm32l051x6/8 devices (see table 9 for differences). tim2 tim2 is based on 16-bit auto-reload up/down counter. it includes a 16-bit prescaler. it features four independent channels each for input capture/output compare, pwm or one- pulse mode output. the tim2 general-purpose timers can work to gether or with the tim21 and tim22 general- purpose timers via the timer link feature for synchronization or event chaining. their counter can be frozen in debug mode. any of the general-purpose timers can be used to generate pwm outputs. tim2 has independent dma request generation. this timer is capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. tim21 and tim22 tim21 and tim22 are based on a 16-bit auto-r eload up/down counter. they include a 16-bit prescaler. they have two independent channels for input capture/output compare, pwm or one-pulse mode output. they can work together and be synchronized with the tim2, full- featured general-purpose timers. they can also be used as simple time bases and be clocked by the lse clock source (32.768 khz) to provide time bases independent from the main cpu clock. table 9. timer feature comparison timer counter resolution counter type prescaler factor dma request generation capture/compare channels complementary outputs tim2 16-bit up, down, up/down any integer between 1 and 65536 yes 4 no tim21, tim22 16-bit up, down, up/down any integer between 1 and 65536 no 2 no tim6 16-bit up any integer between 1 and 65536 yes 0 no docid025938 rev 4 29/119 stm32l051x6 stm32l051x8 functional overview 32 3.14.2 low-power timer (lptim) the low-power timer has an independent clock and is running also in stop mode if it is clocked by lse, lsi or an external clock. it is able to wakeup the devices from stop mode. this low-power timer supports the following features: ? 16-bit up counter with 16-bit autoreload register ? 16-bit compare register ? configurable output: pulse, pwm ? continuous / one shot mode ? selectable software / hardware input trigger ? selectable clock source ? internal clock source: l se, lsi, hsi or apb clock ? external clock source over lptim input (working even with no internal clock source running, used by the pulse counter application) ? programmable digital glitch filter ? encoder mode 3.14.3 basic timer (tim6) this timer can be used as a generic 16-bit timebase. 3.14.4 systick timer this timer is dedicated to the os, but could also be used as a standard downcounter. it is based on a 24-bit downcounter with autore load capability and a programmable clock source. it features a maskable system interr upt generation when the counter reaches ?0?. 3.14.5 independent watchdog (iwdg) the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 37 khz internal rc and, as it operates independently of the main clock, it can operate in stop and stan dby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. it is hardware- or software-configurable through the option bytes. the counter can be frozen in debug mode. 3.14.6 window watchdog (wwdg) the window watchdog is based on a 7-bit downcounter that can be set as free-running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrupt capab ility and the counter can be frozen in debug mode. functional overview stm32l051x6 stm32l051x8 30/119 docid025938 rev 4 3.15 communication interfaces 3.15.1 i 2 c bus up to two i 2 c interfaces (i2c1, i2c2) can operate in multimaster or slave modes. all i 2 c interfaces can support standard mode (sm, up to 100 kbit/s), fast mode (fm, up to 400 kbit/s) and fast mode plus (fm+, up to 1 mbit/s) with 20 ma output drive on some i/os. all i 2 c interfaces support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask). they also include programmable analog and digital noise filters. in addition, i2c1 provides hardware support for smbus 2.0 and pmbus 1.1: arp capability, host notify protocol, hardware crc (pec) gener ation/verification, timeouts verifications and alert protocol management. i2c1 also has a clock domain independent from the cpu clock, allowing the i2c1 to wake up the mcu from stop mode on address match. all i2c interfaces can be se rved by the dma controller. refer to table 11 for the differences between i2c interfaces. table 10. comparison of i2c analog and digital filters analog filter digital filter pulse width of suppressed spikes 50 ns programmable length from 1 to 15 i2c peripheral clocks benefits available in stop mode 1. extra filtering capability vs. standard requirements. 2. stable length drawbacks variations depending on temperature, voltage, process wakeup from stop on address match is not available when digital filter is enabled. table 11. stm32l051x6/8 i 2 c implementation i2c features (1) 1. x = supported. i2c1 i2c2 7-bit addressing mode x x 10-bit addressing mode x x standard mode (up to 100 kbit/s) x x fast mode (up to 400 kbit/s) x x fast mode plus with 20 ma output drive i/os (up to 1 mbit/s) x x (2) 2. see for the list of i/os that feature fast mode plus capability independent clock x - smbus x - wakeup from stop x - docid025938 rev 4 31/119 stm32l051x6 stm32l051x8 functional overview 32 3.15.2 universal synchronous/asynchr onous receiver tran smitter (usart) the two usart interfaces (usart1, usart2) are able to communicate at speeds of up to 4 mbit/s. they provide hardware management of the cts, rts and rs485 driver enable (de) signals, multiprocessor co mmunication mode, master synchronous communication and single-wire half-duplex communication mode. they also support smartcard communication (iso 7816), irda sir endec, lin master/slave capability, auto baud rate feature and has a clock domain independent from the cpu clock, allowing to wake up the mcu from stop mode. all usart interfaces can be served by the dma controller. table 12 for the supported modes and features of usart interfaces. 3.15.3 low-power universal asynchron ous receiver transmitter (lpuart) the devices embed one low-power uart. the lpuart supports asynchronous serial communication with minimum power consumption. it supports half duplex single wire communication and modem operations (c ts/rts). it allows multiprocessor communication. the lpuart has a clock domain independent from the cpu clock, and can wake up the system from stop mode. the wakeup events from stop mode are programmable and can be: ? start bit detection ? or any received data frame ? or a specific programmed data frame only a 32.768 khz clock (lse) is needed to allow lpuart communication up to 9600 baud. therefore, even in stop mode, the lpuart can wait for an incoming frame while table 12. usart implementation usart modes/features (1) 1. x = supported. usart1 and usart2 hardware flow control for modem x continuous communication using dma x multiprocessor communication x synchronous mode x smartcard mode x single-wire half-duplex communication x irda sir endec block x lin mode x dual clock domain and wakeup from stop mode x receiver timeout interrupt x modbus communication x auto baud rate detection (4 modes) x driver enable x functional overview stm32l051x6 stm32l051x8 32/119 docid025938 rev 4 having an extremely low energy consumption. higher speed clock can be used to reach higher baudrates. lpuart interface can be served by the dma controller. 3.15.4 serial peripheral interface (spi)/inter-integrated sound (i2s) up to two spis are able to communicate at up to 16 mbits/s in slave and master modes in full-duplex and half-duplex communication mo des. the 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. the hardware crc generation/verification support s basic sd card/mmc modes. one standard i2s interfaces (multi plexed with spi2) is available. it can operate in master or slave mode, and can be configured to operate wit h a 16-/32-bit resolution as input or output channels. audio sampling frequencies from 8 khz up to 192 khz are supported. when the i2s interfaces is configured in master mode, th e master clock can be output to the external dac/codec at 256 times the sampling frequency. the spis can be served by the dma controller. refer to table 13 for the differences between spi1 and spi2. 3.16 cyclic redundancy che ck (crc) calculation unit the crc (cyclic redundancy check) calculati on unit is used to get a crc code using a configurable generator polynomial value and size. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc calculation unit helps compute a signature of the software during runtime, to be compar ed with a reference signature generated at linktime and stored at a given memory location. 3.17 serial wire debug port (sw-dp) an arm sw-dp interface is provided to allow a serial wire debugging tool to be connected to the mcu. table 13. spi/i2s implementation spi features (1) 1. x = supported. spi1 spi2 hardware crc calculation x x rx/tx fifo x x nss pulse mode x x i2s mode - x ti mode x x docid025938 rev 4 33/119 stm32l051x6 stm32l051x8 pin descriptions 44 4 pin descriptions figure 3. stm32l051x6/8 wlcsp36 ballout 1. the above figure shows the package bump view. figure 4. stm32l051x6/8 lqfp32 pinout 1. the above figure shows the package top view. 3 $ 3 $ 0 6 y 9 $ % & ' ( ) 3 $ 3 $ 3 $ 9 ' ' 3 $ 3 $ 3 $ 3 % 3 % 3 % 3 % 3 % 9 ' ' 3 & 2 6 & b , 1 3 % 3 % 3 % 3 & 2 6 & b 2 8 7 3 % 3 % % 2 2 7 1 5 6 7 3 % 3 $ 9 ' ' $ 9 6 6 3 $ 3 $ 3 $ 9 5 ( ) 3 $ 3 $ 3 $ 3 $ 0 6 y 9 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 9 6 6 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 9 ' ' 1 5 6 7 9 ' ' $ 3 $ 3 $ 3 $ 9 6 6 % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 $ 3 & 2 6 & b , 1 3 & 2 6 & b 2 8 7 9 ' ' 4 ) 1 pin descriptions stm32l051x6 stm32l051x8 34/119 docid025938 rev 4 figure 5. stm32l051x6/8 ufqfpn32 pinout 1. the above figure shows the package top view. figure 6. stm32l051x6/8 lqfp48 pinout - 7 x 7 mm 1. the above figure shows the package top view. 0 6 9 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 3 % 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 9 ' ' 1 5 6 7 9 ' ' $ 3 $ 3 $ 3 $ 3 % % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 $ 3 & 2 6 & b , 1 3 & 2 6 & b 2 8 7 9 ' ' 9 6 6 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 3 % 3 % 3 % 9 6 6 9 ' ' 9 ' ' 9 6 6 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 3 % 3 % 9 ' ' 3 & 3 & 2 6 & b , 1 3 & 2 6 & b 2 8 7 3 + 2 6 & b , 1 3 + 2 6 & b 2 8 7 1 5 6 7 9 6 6 $ 9 ' ' $ 3 $ 3 $ 3 $ 9 ' ' 9 6 6 3 % 3 % % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 $ 3 $ / 4 ) 3 0 6 9 docid025938 rev 4 35/119 stm32l051x6 stm32l051x8 pin descriptions 44 figure 7. stm32l051x6/8 lqfp64 pinout - 10 x 10 mm 1. the above figure shows the package top view. 9 ' ' 3 & 3 & 2 6 & b , 1 3 & 2 6 & b 2 8 7 3 + 2 6 & b , 1 3 + 2 6 & b 2 8 7 1 5 6 7 3 & 3 & 3 & 3 & 9 6 6 $ 9 ' ' $ 3 $ 3 $ 3 $ 9 ' ' 9 6 6 3 % 3 % % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 ' 3 & 3 & 3 & 3 $ 3 $ 9 ' ' 9 6 6 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 & 3 & 3 % 3 % 3 % 3 % 3 $ 9 6 6 9 ' ' 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 % 3 % 3 % 3 % 3 % 9 6 6 9 ' ' / 4 ) 3 0 6 9 pin descriptions stm32l051x6 stm32l051x8 36/119 docid025938 rev 4 figure 8. stm32l051x6/8 tfbga64 ballout - 5x 5 mm 1. the above figure shows the package bump view. 3 + 2 6 & b , 1 3 & 2 6 & b , 1 0 6 y 9 $ % & ' ( ) * + 3 & 2 6 & b 2 8 7 3 + 2 6 & b 2 8 7 1 5 6 7 9 6 6 $ 9 5 ( ) 9 ' ' $ 3 & 9 ' ' 9 6 6 9 ' ' 3 & 3 & 3 $ 3 $ 3 % 3 % 3 % 3 $ 3 $ 3 $ 3 % % 2 2 7 3 ' 3 & 3 & 3 $ 3 % 3 % 3 & 3 $ 3 $ 3 $ 3 % 9 6 6 9 6 6 9 6 6 3 $ 3 & 3 & 9 ' ' 9 ' ' 9 ' ' 3 & 3 & 3 $ 3 $ 3 % 3 & 3 % 3 % 3 $ 3 $ 3 % 3 % 3 % 3 % 3 $ 3 $ 3 & 3 & 3 % 3 % table 14. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets be low the pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input / output pin i/o structure ft 5 v tolerant i/o tc standard 3.3v i/o b dedicated boot0 pin rst bidirectional reset pin with embedded weak pull-up resistor notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset. pin functions alternate functions functions selected through gpiox_afr registers additional functions functions directly selected/enabl ed through peripheral registers docid025938 rev 4 37/119 stm32l051x6 stm32l051x8 pin descriptions 44 table 15. stm32l051x6/8 pin definitions pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions lqfp32 ufqfpn32 (1) wlcsp36 (2) lqfp48 lqfp64 tfbga64 -- -11b2 vdd s -- -22a2 pc13- anti_tamp i/o ft rtc_tamp1/ rtc_ts/ rtc_out/ wkup2 2 2 a6 3 3 a1 pc14- osc32_in i/o ft osc32_in 3 3 b6 4 4 b1 pc15- osc32_out i/o tc osc32_out - - - 5 5 c1 ph0-osc_in i/o tc osc_in -- -66d1 ph1- osc_out i/o tc osc_out 4 4 c6 7 7 e1 nrst i/o rst - - - - 8 e3 pc0 i/o ft lptim1_in1, eventout adc_in10 - - - - 9 e2 pc1 i/o ft lptim1_out, eventout adc_in11 - - - - 10 f2 pc2 i/o ft lptim1_in2, spi2_miso/i2s2_mck adc_in12 - - - - 11 - pc3 i/o ft lptim1_etr, spi2_mosi/i2s2_sd adc_in13 - - - 8 12 f1 vssa s - - e6 - - g1 vref+ s 5 5 d5 9 13 h1 vdda s 6 6 d4 10 14 g2 pa0 i/o tc tim2_ch1, usart2_cts, tim2_etr, comp1_out comp1_inm6, adc_in0, rtc_tamp2/w kup1 pin descriptions stm32l051x6 stm32l051x8 38/119 docid025938 rev 4 7 7 f6 11 15 h2 pa1 i/o ft eventout, tim2_ch2, usart2_rts, tim21_etr comp1_inp, adc_in1 8 8 e5 12 16 f3 pa2 i/o ft tim21_ch1, tim2_ch3, usart2_tx, comp2_out comp2_inm6, adc_in2 9 9 f5 13 17 g3 pa3 i/o ft tim21_ch2, tim2_ch4, usart2_rx comp2_inp, adc_in3 - - - - 18 c2 vss s -- - -19d2 vdd s 10 10 e4 14 20 h3 pa4 i/o tc (3) spi1_nss, usart2_ck, tim22_etr comp1_inm4, comp2_inm4, adc_in4 11 11 f4 15 21 f4 pa5 i/o tc spi1_sck, tim2_etr, tim2_ch1 comp1_inm5, comp2_inm5, adc_in5 12 12 e3 16 22 g4 pa6 i/o ft spi1_miso, lpuart1_cts, tim22_ch1, eventout, comp1_out adc_in6 13 13 f3 17 23 h4 pa7 i/o ft spi1_mosi, tim22_ch2, eventout, comp2_out adc_in7 - - - - 24 h5 pc4 i/o ft eventout, lpuart1_tx adc_in14 - - - - 25 h6 pc5 i/o tc lpuart1_rx, adc_in15 14 14 d3 18 26 f5 pb0 i/o ft eventout adc_in8, vref_out 15 15 c3 19 27 g5 pb1 i/o ft lpuart1_rts adc_in9, vref_out table 15. stm32l051x6/8 pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions lqfp32 ufqfpn32 (1) wlcsp36 (2) lqfp48 lqfp64 tfbga64 docid025938 rev 4 39/119 stm32l051x6 stm32l051x8 pin descriptions 44 - 16 f2 20 28 g6 pb2 i/o ft lptim1_out - - e2 21 29 g7 pb10 i/o ft tim2_ch3, lpuart1_tx, spi2_sck, i2c2_scl - - d2 22 30 h7 pb11 i/o ft eventout, tim2_ch4, lpuart1_rx, i2c2_sda 16 - - 23 31 d6 vss s 17 17 f1 24 32 e6 vdd s - - - 25 33 h8 pb12 i/o ft spi2_nss/i2s2_ws, lpuart1_rts, i2c2_smba, eventout - - - 26 34 g8 pb13 i/o ftf spi2_sck/i2s2_ck, lpuart1_cts, i2c2_scl, tim21_ch1 - - - 27 35 f8 pb14 i/o ftf spi2_miso/i 2s2_mck, rtc_out, lpuart1_rts, i2c2_sda, tim21_ch2 - - - 28 36 f7 pb15 i/o ft spi2_mosi/i2s2_sd, rtc_refin - - - - 37 f6 pc6 i/o ft tim22_ch1 - - - - 38 e7 pc7 i/o ft tim22_ch2 - - - - 39 e8 pc8 i/o ft tim22_etr - - - - 40 d8 pc9 i/o ft tim21_etr 18 18 e1 29 41 d7 pa8 i/o ft mco, eventout, usart1_ck 19 19 d1 30 42 c7 pa9 i/o ft mco, usart1_tx table 15. stm32l051x6/8 pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions lqfp32 ufqfpn32 (1) wlcsp36 (2) lqfp48 lqfp64 tfbga64 pin descriptions stm32l051x6 stm32l051x8 40/119 docid025938 rev 4 20 20 c1 31 43 c6 pa10 i/o ft usart1_rx 21 21 c2 32 44 c8 pa11 i/o ft spi1_miso, eventout, usart1_cts, comp1_out 22 22 b1 33 45 b8 pa12 i/o ft spi1_mosi, eventout, usart1_rts, comp2_out 23 23 a1 34 46 a8 pa13 i/o ft swdio - - - 35 47 d5 vss s - - - 36 48 e5 vddio2 s 24 24 b2 37 49 a7 pa14 i/o ft swclk, usart2_tx 25 25 a2 38 50 a6 pa15 i/o ft spi1_nss, tim2_etr, eventout, usart2_rx, tim2_ch1 - - - - 51 b7 pc10 i/o ft lpuart1_tx - - - - 52 b6 pc11 i/o ft lpuart1_rx - - - - 53 c5 pc12 i/o ft - - - - 54 b5 pd2 i/o ft lpuart1_rts 26 26 b3 39 55 a5 pb3 i/o ft spi1_sck, tim2_ch2, eventout comp2_inn 27 27 a3 40 56 a4 pb4 i/o ft spi1_miso, eventout, tim22_ch1 comp2_inp 28 28 c4 41 57 c4 pb5 i/o ft spi1_mosi, lptim1_in1, i2c1_smba, tim22_ch2 comp2_inp table 15. stm32l051x6/8 pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions lqfp32 ufqfpn32 (1) wlcsp36 (2) lqfp48 lqfp64 tfbga64 docid025938 rev 4 41/119 stm32l051x6 stm32l051x8 pin descriptions 44 29 29 b4 42 58 d3 pb6 i/o ftf usart1_tx, i2c1_scl, lptim1_etr comp2_inp 30 30 a4 43 59 c3 pb7 i/o ftf usart1_rx, i2c1_sda, lptim1_in2 comp2_inp, pvd_in 31 31 c5 44 60 b4 boot0 b - 32b54561b3 pb8 i/oftf i2c1_scl - - - 46 62 a3 pb9 i/o ftf eventout, i2c1_sda, spi2_nss/i2s2_ws 32 - d64763d4 vss s 1 1 a5 48 64 e4 vdd s 1. vss pins are connected to the exposed pad (see figure 40: ufqfpn32, 5 x 5 mm, 32-pin package outline ). 2. pb9/12/13/14/15, ph0/1 and pc13 gpios should be configured as output and driven low, even if they are not available on this package. 3. pa4 offers a reduced touch sensing sensitivity. it is thus recommended to use it as sampling capacitor i/o. table 15. stm32l051x6/8 pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions lqfp32 ufqfpn32 (1) wlcsp36 (2) lqfp48 lqfp64 tfbga64 pin descriptions stm32l051x6 stm32l051x8 42/119 docid025938 rev 4 table 16. alternate function port a port af0 af1 af2 af3 af4 af5 af6 af7 spi1/tim21/sys_a f/eventout/ - tim2/ eventout/ eventout usart1/2/3 tim2/21/22 eventout comp1/2 port a pa0 tim2_ch1 usart2_cts tim2_etr comp1_out pa1 eventout tim2_ch2 usart2_rts tim21_etr pa2 tim21_ch1 tim2_ch3 usart2_tx comp2_out pa3 tim21_ch2 tim2_ch4 usart2_rx pa4 spi1_nss usart2_ck tim22_etr pa5 spi1_sck tim2_etr tim2_ch1 pa6 spi1_miso lpuart1_ct s tim22_ch1 eventout comp1_out pa7 spi1_mosi tim22_ch2 eventout comp2_out pa8 mco eventout usart1_ck pa9 mco usart1_tx pa10 usart1_rx pa11 spi1_miso eventout usart1_cts comp1_out pa12 spi1_mosi eventout usart1_rts comp2_out pa13 swdio pa14 swclk usart2_tx pa15 spi1_nss tim2_etr eventout usart2_rx tim2_ch1 stm32l051x6 stm32l051x8 pin descriptions docid025938 rev 4 43/119 table 17. alternate function port b port af0 af1 af2 af3 af4 af5 af6 spi1/spi2/i2s2/ usart1/ eventout/ i2c1 lpuart1/lptim /tim2/sys_af/ eventout i2c1 i2c1/tim22/ eventout/ lpuart1 spi2/i2s2/i2c2 i2c2/tim21/ eventout port b pb0 eventout pb1 lpuart1_rts pb2 lptim1_out pb3 spi1_sck tim2_ch2 eventout pb4 spi1_miso eventout tim22_ch1 pb5 spi1_mosi lptim1_in1 i2c1_smba tim22_ch2 pb6 usart1_tx i2c1_scl lptim1_etr pb7 usart1_rx i2c1_sda lptim1_in2 pb8 i2c1_scl pb9 eventout i2c1_sda spi2_nss/i2s2_ ws pb10 tim2_ch3 lpuart1_tx spi2_sck i2c2_scl pb11 eventout tim2_ch4 lpuart1_rx i2c2_sda pb12 spi2_nss/i2s2_ws lpuar t1_rts i2c2_smba eventout pb13 spi2_sck/i2s2_ck lpuar t1_cts i2c2_scl tim21_ch1 pb14 spi2_miso/i2s2_mck rtc_out lpuart1_rts i2c2_sda tim21_ch2 pb15 spi2_mosi/i2s2_sd rtc_refin pin descriptions stm32l051x6 stm32l051x8 44/119 docid025938 rev 4 table 18. alternate function port c port af0 af1 af2 lpuart1/lptim/tim21/12/eventout - spi2/i2s2/lpuart1/eventout port c pc0 lptim1_in1 eventout pc1 lptim1_out eventout pc2 lptim1_in2 spi2_miso/i2s2_mck pc3 lptim1_etr spi2_mosi/i2s2_sd pc4 eventout lpuart1_tx pc5 lpuart1_rx pc6 tim22_ch1 pc7 tim22_ch2 pc8 tim22_etr pc9 tim21_etr pc10 lpuart1_tx pc11 lpuart1_rx pc12 pc13 pc14 pc15 table 19. alternate function port d port af0 af1 lpuart1 - port d pd2 lpuart1_rts docid025938 rev 4 45/119 stm32l051x6 stm32l051x8 memory mapping 45 5 memory mapping figure 9. memory map 0 6 9 5 h v h u y h g ) / 0 / 2 4 [ ) ) ) ) ) ) ) ) 3 h u l s k h u d o v 6 5 $ 0 ) o d v k v \ v w h p p h p r u \ r e s e r v e d 6 \ v w h p p h p r u \ 2 s w l r q e \ w h v [ ( & l a s h s y s t e m m e m o r y o r 3 2 ! - d e m e n d i n g o n " / / 4 c o n f i g u r a t i o n [ [ ( [ & [ $ [ [ [ [ [ [ [ ) ) ) ) ) ) ) r e s e r v e d & 2 ' ( ! 0 " ! 0 " r e s e r v e d [ [ [ [ r e s e r v e d [ ! ( " [ r e s e r v e d [ ) ) ) [ ) ) & r u w h [ 0 s h u l s k h u d o v electrical characteristics stm32l051x6 stm32l051x8 46/119 docid025938 rev 4 6 electrical characteristics 6.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 6.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 6.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3.6 v (for the 1.65 v v dd 3.6 v voltage range). they are given on ly as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 6.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 10 . 6.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 11 . figure 10. pin loading conditions figure 11. pin input voltage d l f & s ) 0 & 8 s l q d l f 0 & 8 s l q 9 , 1 docid025938 rev 4 47/119 stm32l051x6 stm32l051x8 electrical characteristics 97 6.1.6 power supply scheme figure 12. power supply scheme 6.1.7 current consumption measurement figure 13. current consum ption measurement scheme 0 6 y 9 $ q d o r j 5 & 3 / / & 2 0 3 ? 9 ' ' * 3 , 2 v 2 8 7 , 1 . h u q h o o r j l f & 3 8 ' l j l w d o 0 h p r u l h v 6 w d q g e \ s r z h u f l u f x l w u \ 2 6 & 5 7 & : d n h x s o r j l f 5 7 & e d f n x s u h j l v w h u v 1 ? q ) ? ? ) 5 h j x o d w r u 9 6 6 9 ' ' $ 9 5 ( ) 9 5 ( ) 9 6 6 $ $ ' & / h y h o v k l i w h u , 2 / r j l f 9 ' ' q ) ? ) 9 5 ( ) q ) ? ) 9 ' ' $ 0 6 y 9 1 [ 9 ' ' , ' ' 1 ? q ) ? ? ) 1 [ 9 6 6 9 ' ' $ electrical characteristics stm32l051x6 stm32l051x8 48/119 docid025938 rev 4 6.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 20: voltage characteristics , table 21: current characteristics , and table 22: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may af fect device reliability. table 20. voltage characteristics symbol ratings min max unit v dd ?v ss external main supply voltage (including v dda , v ddio2 , v dd ) (1) 1. all main power (v dd , v ddio2 , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. ?0.3 4.0 v v in (2) 2. v in maximum must always be respected. refer to table 21 for maximum allowed injected current values. input voltage on ft and ftf pins v ss ? 0.3 v dd +4.0 input voltage on tc pins v ss ? 0.3 4.0 input voltage on boot0 v ss v dd + 4.0 input voltage on any other pin v ss ? 0.3 4.0 | v dd | variations between different v dd /v dda power pins (3) 3. it is recommended to power v dd and v dda from the same source. a maximum difference of 300 mv between v dd and v dda can be tolerated during power-up and device operation. v ddio2 is independent from v dd and v dda : its value does not need to respect this rule. -50 mv | v ss | variations between all different ground pins - 50 v ref+ ?v dda allowed voltage difference for v ref+ > v dda -0.4v v esd(hbm) electrostatic discharge voltage (human body model) see section 6.3.11 docid025938 rev 4 49/119 stm32l051x6 stm32l051x8 electrical characteristics 97 table 21. current characteristics symbol ratings max. unit i vdd (2) total current into sum of all v dd power lines (source) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. 105 ma i vss (2) 2. this current consumption must be correctly distri buted over all i/os and control pins. the total output current must not be sunk/sourced between two consecut ive power supply pins referring to high pin count lqfp packages. total current out of sum of all v ss ground lines (sink) (1) 105 i vdd(pin) maximum current into each v dd power pin (source) (1) 100 i vss(pin) maximum current out of each v ss ground pin (sink) (1) 100 i io output current sunk by any i/o and control pin except ftf pins 16 output current sunk by ftf pins 22 output current sourced by any i/o and control pin -16 i io(pin) total output current sunk by sum of all ios and control pins (2) 90 total output current sourced by sum of all ios and control pins (2) -90 i inj(pin) injected current on ft, fff, rst and b pins -5/+0 (3) 3. positive current injection is not possible on these i/os. a negative injection is induced by v in electrical characteristics stm32l051x6 stm32l051x8 50/119 docid025938 rev 4 6.3 operating conditions 6.3.1 general operating conditions table 23. general operating conditions symbol parameter conditions min max unit f hclk internal ahb clock frequency - 0 32 mhz f pclk1 internal apb1 clock frequency - 0 32 f pclk2 internal apb2 clock frequency - 0 32 v dd standard operating voltage bor detector disabled 1.65 3.6 v bor detector enabled, at power on 1.8 3.6 bor detector disabled, after power on 1.65 3.6 v dda analog operating voltage (all features) must be the same voltage as v dd (1) 1.8 3.6 v v ddio2 standard operating voltage 1.65 3.6 v v in input voltage on ft, ftf and rst pins (2) 2.0 v v dd 3.6 v -0.3 5.5 v 1.65 v v dd 2.0 v -0.3 5.2 input voltage on boot0 pin - 0 5.5 input voltage on tc pin - -0.3 v dd +0.3 p d power dissipation at t a = 85 c (range 6) or t a =105 c (rage 7) (3) tfbga64 package - 327 mw lqfp64 package - 444 lqfp48 package - 363 wlcsp36 package - 318 lqfp32 package - 526 ufqfpn32 - 351 power dissipation at t a = 125 c (range 3) (3) tfbga64 package - 81 lqfp64 package - 111 lqfp48 package - 91 wlcsp36 package - 79 lqfp32 package - 88 ufqfpn32 - 132 docid025938 rev 4 51/119 stm32l051x6 stm32l051x8 electrical characteristics 97 6.3.2 embedded reset and power control block characteristics the parameters given in the following table are derived from the tests performed under the ambient temperature condition summarized in table 23 . t a temperature range maximum power dissipation (range 6) ?40 85 c maximum power dissipation (range 7) ?40 105 maximum power dissipation (range 3) ?40 125 t j junction temperature range (range 6) -40 c t a 85 ?40 105 junction temperature range (range 7) -40 c t a 105 c ?40 125 junction temperature range (range 3) -40 c t a 125 c ?40 130 1. it is recommended to power v dd and v dda from the same source. a maximum difference of 300 mv between v dd and v dda can be tolerated during power-up and normal operation. 2. to sustain a voltage higher than v dd +0.3v, the internal pull-up/pull-down resistors must be disabled. 3. if t a is lower, higher p d values are allowed as long as t j does not exceed t j max (see table 22: thermal characteristics on page 49 ). table 23. general operating conditions (continued) symbol parameter conditions min max unit table 24. embedded reset and power control block characteristics symbol parameter conditions min typ max unit t vdd (1) v dd rise time rate bor detector enabled 0 - s/v bor detector disabled 0 - 1000 v dd fall time rate bor detector enabled 20 - bor detector disabled 0 - 1000 t rsttempo (1) reset temporization v dd rising, bor enabled - 2 3.3 ms v dd rising, bor disabled (2) 0.4 0.7 1.6 v por/pdr power on/power down reset threshold falling edge 1 1.5 1.65 v rising edge 1.3 1.5 1.65 v bor0 brown-out reset threshold 0 falling edge 1.67 1.7 1.74 rising edge 1.69 1.76 1.8 v bor1 brown-out reset threshold 1 falling edge 1.87 1.93 1.97 rising edge 1.96 2.03 2.07 v bor2 brown-out reset threshold 2 falling edge 2.22 2.30 2.35 rising edge 2.31 2.41 2.44 electrical characteristics stm32l051x6 stm32l051x8 52/119 docid025938 rev 4 v bor3 brown-out reset threshold 3 falling edge 2.45 2.55 2.6 v rising edge 2.54 2.66 2.7 v bor4 brown-out reset threshold 4 falling edge 2.68 2.8 2.85 rising edge 2.78 2.9 2.95 v pvd0 programmable voltage detector threshold 0 falling edge 1.8 1.85 1.88 rising edge 1.88 1.94 1.99 v pvd1 pvd threshold 1 falling edge 1.98 2.04 2.09 rising edge 2.08 2.14 2.18 v pvd2 pvd threshold 2 falling edge 2.20 2.24 2.28 rising edge 2.28 2.34 2.38 v pvd3 pvd threshold 3 falling edge 2.39 2.44 2.48 rising edge 2.47 2.54 2.58 v pvd4 pvd threshold 4 falling edge 2.57 2.64 2.69 rising edge 2.68 2.74 2.79 v pvd5 pvd threshold 5 falling edge 2.77 2.83 2.88 rising edge 2.87 2.94 2.99 v pvd6 pvd threshold 6 falling edge 2.97 3.05 3.09 rising edge 3.08 3.15 3.20 v hyst hysteresis voltage bor0 threshold - 40 - mv all bor and pvd thresholds excepting bor0 -100- 1. guaranteed by characterization results, not tested in production. 2. valid for device version without bor at power up. please see option "d" in orderi ng information scheme for more details. table 24. embedded reset and power control block characteristics (continued) symbol parameter conditions min typ max unit docid025938 rev 4 53/119 stm32l051x6 stm32l051x8 electrical characteristics 97 6.3.3 embedded internal reference voltage the parameters given in table 26 are based on characterization results, unless otherwise specified. table 25. embedded internal reference voltage calibration values calibration value name description memory address vrefint_cal raw data acquired at temperature of 30 c v dda = 3 v 0x1ff8 0078 - 0x1ff8 0079 table 26. embedded internal reference voltage (1) symbol parameter conditions min typ max unit v refint out (2) internal reference voltage ? 40 c < t j < +125 c 1.202 1.224 1.242 v t vrefint internal reference startup time - - 2 3 ms v vref_meas v dda and v ref+ voltage during v refint factory measure -2.9933.01v a vref_meas accuracy of factory-measured v ref value (3) including uncertainties due to adc and v dda /v ref+ values -- 5mv t coeff (4) temperature coefficient ?40 c < t j < +125 c - 20 50 ppm/c 0 c < t j < +50 c - - 20 a coeff (4) long-term stability 1000 hours, t= 25 c - - 1000 ppm v ddcoeff (4) voltage coefficient 3.0 v < v dda < 3.6 v - - 2000 ppm/v t s_vrefint (4)(5) adc sampling time when reading the internal reference voltage -510-s t adc_buf (4) startup time of reference voltage buffer for adc ---10s i buf_adc (4) consumption of reference voltage buffer for adc - - 13.5 25 a i vref_out (4) vref_out output current (6) ---1a c vref_out (4) vref_out output load - - - 50 pf i lpbuf (4) consumption of reference voltage buffer for vref_out and comp - - 730 1200 na v refint_div1 (4) 1/4 reference voltage - 24 25 26 % v refint v refint_div2 (4) 1/2 reference voltage - 49 50 51 v refint_div3 (4) 3/4 reference voltage - 74 75 76 1. refer to table 38: peripheral current c onsumption in stop and standby mode for the value of the internal reference current consumption (i refint ). 2. guaranteed by test in production. 3. the internal v ref value is individually measured in produc tion and stored in dedicated eeprom bytes. electrical characteristics stm32l051x6 stm32l051x8 54/119 docid025938 rev 4 6.3.4 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, temperature, i/o pin loadi ng, device software conf iguration, operating frequencies, i/o pin switching rate, program lo cation in memory and executed binary code. the current consumption is measured as described in figure 13: current consumption measurement scheme . all run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equival ent to dhrystone 2.1 code if not specified otherwise. the current consumption values are derived from the tests performed under ambient temperature and v dd supply voltage conditions summarized in table 23: general operating conditions unless otherwis e specified. the mcu is placed under the following conditions: ? all i/o pins are configured in analog input mode ? all peripherals are disabled ex cept when explicitly mentioned ? the flash memory access time and prefetch is adjusted depending on fhclk frequency and voltage range to provide t he best cpu performance unless otherwise specified. ? when the peripherals are enabled f apb1 = f apb2 = f apb ? when pll is on, the pll inputs are equal to hsi = 16 mhz (if internal clock is used) or hse = 16 mhz (if hse bypass mode is used) ? the hse user clock applied to osci_in input follows the characteristic specified in table 40: high-speed external user clock characteristics ? for maximum current consumption v dd = v dda = 3.6 v is applied to all supply pins ? for typical current consumption v dd = v dda = 3.0 v is applied to all supply pins if not specified otherwise the parameters given in table 47 , table 23 and table 24 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 23 . 4. guaranteed by design, not tested in production. 5. shortest sampling time can be determined in the application by multiple iterations. 6. to guarantee less than 1% vref_out deviation. docid025938 rev 4 55/119 stm32l051x6 stm32l051x8 electrical characteristics 97 table 27. current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk typ max (1) unit i dd (run from flash) supply current in run mode, code executed from flash f hse = f hclk up to 16 mhz included, f hse = f hclk /2 above 16 mhz (pll on) (2) range 3, v core =1.2 v vos[1:0]=11 1 mhz 165 230 a 2 mhz 290 360 4 mhz 555 630 range 2, v core =1.5 v, vos[1:0]=10, 4 mhz 0.665 0.74 ma 8 mhz 1.3 1.4 16 mhz 2.6 2.8 range 1, v core =1.8 v, vos[1:0]=01 8 mhz 1.55 1.7 16 mhz 3.1 3.4 32 mhz 6.3 6.8 msi clock range 3, v core =1.2 v, vos[1:0]=11 65 khz 36.5 110 a 524 khz 99.5 190 4.2 mhz 620 700 hsi clock range 2, v core =1.5 v, vos[1:0]=10, 16 mhz 2.6 2.9 ma range 1, v core =1.8 v, vos[1:0]=01 32 mhz 6.25 7 1. guaranteed by characterization re sults at 125 c, not tested in production, unless otherwise specified. 2. oscillator bypassed (hsebyp = 1 in rcc_cr register). table 28. current consumption in run mode vs code type, code with data processing running from flash symbol parameter conditions f hclk typ unit i dd (run from flash) supply current in run mode, code executed from flash f hse = f hclk up to 16 mhz included, f hse = f hclk /2 above 16 mhz (pll on) (1) range 3, v core =1.2 v, vos[1:0]=11 dhrystone 4 mhz 555 a coremark 585 fibonacci 440 while(1) 355 while(1), prefetch off 353 range 1, vos[1:0]=01, v core =1.8 v dhrystone 32 mhz 6.3 ma coremark 6.3 fibonacci 6.55 while(1) 5.4 while(1), prefetch off 5.2 1. oscillator bypassed (hsebyp = 1 in rcc_cr register). electrical characteristics stm32l051x6 stm32l051x8 56/119 docid025938 rev 4 figure 14. i dd vs v dd , at t a = 25/55/85/105 c, run mode, code running from flash memory, range 2, hse, 1ws figure 15. i dd vs v dd , at t a = 25/55/85/105 c, run mode, code running from flash memory, range 2, hsi16, 1ws 0 6 y 9 z????}v ?x r t ^ r ?? z????}v ?xr t ^ r ?? z????}v ?xr t ^ t ?? z????}v ?xr t ^ r ? x? x x? ?x ?x? ?x x? = ?x = ?x? = ?xe = ?x = ?x? = ?x = ?x? = ?xe = ?x = / ~u s ~ s 0 6 y 9 , ' ' p $ 9 ' ' 9 ' k u \ v w r q h : 6 ? & ' k u \ v w r q h : 6 ? & ' k u \ v w r q h : 6 ? & z????}v ?xr t ^ r ? x? x x? ?x ?x? ?x ( ( ( ( ( ( ( ( ( ( docid025938 rev 4 57/119 stm32l051x6 stm32l051x8 electrical characteristics 97 table 29. current consumption in run mode, code with data processing running from ram symbol parameter conditions f hclk typ max (1) unit i dd (run from ram) supply current in run mode, code executed from ram, flash switched off f hse = f hclk up to 16 mhz, included f hse = f hclk /2 above 16 mhz (pll on) (2) range 3, v core =1.2 v, vos[1:0]=11 1 mhz 135 170 a 2 mhz 240 270 4 mhz 450 480 range 2, v core =1.5 ,v, vos[1:0]=10 4 mhz 0.52 0.6 ma 8 mhz 1 1.2 16 mhz 2 2.3 range 1, v core =1.8 v, vos[1:0]=01 8 mhz 1.25 1.4 16 mhz 2.45 2.8 32 mhz 5.1 5.4 msi clock range 3, v core =1.2 v, vos[1:0]=11 65 khz 34.5 75 a 524 khz 83 120 4.2 mhz 485 540 hsi16 clock source (16 mhz) range 2, v core =1.5 v, vos[1:0]=10 16 mhz 2.1 2.3 ma range 1, v core =1.8 v, vos[1:0]=01 32 mhz 5.1 5.6 1. guaranteed by char acterization results at 125 c , not tested in production, unless otherwise specified. 2. oscillator bypassed (hsebyp = 1 in rcc_cr register). table 30. current consumption in run mode vs code type, code with data processing running from ram (1) symbol parameter conditions f hclk typ unit i dd (run from ram) supply current in run mode, code executed from ram, flash switched off f hse = f hclk up to 16 mhz, included, f hse = f hclk /2 above 16 mhz (pll on) (2) range 3, v core =1.2 v, vos[1:0]=11 dhrystone 4 mhz 450 a coremark 575 fibonacci 370 while(1) 340 range 1, v core =1.8 v, vos[1:0]=01 dhrystone 32 mhz 5.1 ma coremark 6.25 fibonacci 4.4 while(1) 4.7 1. guaranteed by characterization results, not tested in production, unless otherwise specified. 2. oscillator bypassed (hsebyp = 1 in rcc_cr register). electrical characteristics stm32l051x6 stm32l051x8 58/119 docid025938 rev 4 table 31. current consumption in sleep mode symbol parameter conditions f hclk typ max (1) unit i dd (sleep) supply current in sleep mode, flash off f hse = f hclk up to 16 mhz included, f hse = f hclk /2 above 16 mhz (pll on) (2) range 3, v core =1.2 v, vos[1:0]=11 1 mhz 43.5 90 a 2 mhz 72 120 4 mhz 130 180 range 2, v core =1.5 v, vos[1:0]=10 4 mhz 160 210 8 mhz 305 370 16 mhz 590 710 range 1, v core =1.8 v, vos[1:0]=01 8 mhz 370 430 16 mhz 715 860 32 mhz 1650 1900 msi clock range 3, v core =1.2 v, vos[1:0]=11 65 khz 18 65 524 khz 31.5 75 4.2 mhz 140 210 hsi16 clock source (16 mhz) range 2, v core =1.5 v, vos[1:0]=10 16 mhz 665 830 range 1, v core =1.8 v, vos[1:0]=01 32 mhz 1750 2100 supply current in sleep mode, flash on f hse = f hclk up to 16 mhz included, f hse = f hclk /2 above 16 mhz (pll on) (2) range 3, v core =1.2 v, vos[1:0]=11 1 mhz 57.5 130 2 mhz 84 170 4 mhz 150 280 range 2, core =1.5 v, vos[1:0]=10 4 mhz 170 310 8 mhz 315 420 16 mhz 605 770 range 1, v core =1.8 v, vos[1:0]=01 8 mhz 380 460 16 mhz 730 950 32 mhz 1650 2400 msi clock range 3, v core =1.2 v, vos[1:0]=11 65 khz 29.5 110 524 khz 44.5 130 4.2 mhz 150 270 hsi16 clock source (16 mhz) range 2, v core =1.5 v, vos[1:0]=10 16 mhz 680 950 range 1, v core =1.8 v, vos[1:0]=01 32 mhz 1750 2100 1. guaranteed by characterization results at 125 c, not tested in production, unless otherwise specified. 2. oscillator bypassed (hsebyp = 1 in rcc_cr register). docid025938 rev 4 59/119 stm32l051x6 stm32l051x8 electrical characteristics 97 table 32. current consumption in low-power run mode symbol parameter conditions typ max (1) unit i dd (lp run) supply current in low-power run mode all peripherals off, code executed from ram, flash switched off, v dd from 1.65 v to 3.6 v msi clock, 65 khz f hclk = 32 khz t a = -40 c to 25 c 8.5 10 a t a = 85 c 11.5 48 t a = 105 c 15.5 53 t a = 125 c 27.5 130 msi clock, 65 khz f hclk = 65 khz t a =-40 c to 25 c 10 15 t a = 85 c 15.5 50 t a = 105 c 19.5 54 t a = 125 c 31.5 130 msi clock, 131 khz f hclk = 131 khz t a = -40 c to 25 c 20 25 t a = 55 c 23 50 t a = 85 c 25.5 55 t a = 105 c 29.5 64 t a = 125 c 40 140 all peripherals off, code executed from flash, v dd from 1.65 v to 3.6 v msi clock, 65 khz f hclk = 32 khz t a = -40 c to 25 c 22 28 t a = 85 c 26 68 t a = 105 c 31 75 t a = 125 c 44 95 msi clock, 65 khz f hclk = 65 khz t a = -40 c to 25 c 27.5 33 t a = 85 c 31.5 73 t a = 105 c 36.5 80 t a = 125 c 49 100 msi clock, 131 khz f hclk = 131 khz t a = -40 c to 25 c 39 46 t a = 55 c 41 80 t a = 85 c 44 86 t a = 105 c 49.5 100 t a = 125 c 60 120 1. guaranteed by characterization results at 125 c, not tested in production, unless otherwise specified. electrical characteristics stm32l051x6 stm32l051x8 60/119 docid025938 rev 4 figure 16. i dd vs v dd , at t a = 25/55/ 85/105/125 c, low-power run mode, code running from ram, range 3, msi (range 0) at 64 khz, 0 ws 0 6 y 9 : 6 ? & : 6 ? & : 6 ? & : 6 ? & : 6 ? & 9 ' ' 9 , ' ' p $ ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( table 33. current consumption in low-power sleep mode symbol parameter conditions typ max (1) unit i dd (lp sleep) supply current in low-power sleep mode all peripherals off, v dd from 1.65 v to 3.6 v msi clock, 65 khz f hclk = 32 khz flash off t a = -40 c to 25 c 4.7 (2) - a msi clock, 65 khz f hclk = 32 khz flash on t a = -40 c to 25 c 17 23 t a = 85 c 19.5 63 t a = 105 c 23 69 t a = 125 c 32.5 90 msi clock, 65 khz f hclk = 65 khz, flash on t a = -40 c to 25 c 17 23 t a = 85 c 20 63 t a = 105 c 23.5 69 t a = 125 c 32.5 90 msi clock, 131 khz f hclk = 131 khz, flash on t a = -40 c to 25 c 19.5 36 t a = 55 c 20.5 64 t a = 85 c 22.5 66 t a = 105 c 26 72 t a = 125 c 35 95 1. guaranteed by characterization results at 125 c, not tested in production, unless otherwise specified. 2. as the cpu is in sleep mode, the difference between the current consumption with flash on and off (nearly 12 a) is the same whatever the clock frequency. docid025938 rev 4 61/119 stm32l051x6 stm32l051x8 electrical characteristics 97 figure 17. i dd vs v dd , at t a = 25/55/ 85/105/125 c, stop mode with rtc enabled and running on lse low drive figure 18. i dd vs v dd , at t a = 25/55/85/105/125 c, stop mode with rtc disabled, all clocks off table 34. typical and maximum current consumptions in stop mode symbol parameter conditions typ max (1) 1. guaranteed by characterization results at 125 c, not tested in production, unless otherwise specified. unit i dd (stop) supply current in stop mode t a = -40c to 25c 0.41 1 a t a = 55c 0.63 2.1 t a = 85c 1.7 4.5 t a = 105c 4 9.6 t a = 125c 11 24 (2) 2. guaranteed by test in production. 0 6 y 9 , ' ' p $ 9 ' ' 9 ? & ? & ? & ? & ? & ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( 0 6 y 9 , ' ' p $ ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( 9 ' ' 9 ? & ? & ? & ? & ? & electrical characteristics stm32l051x6 stm32l051x8 62/119 docid025938 rev 4 on-chip peripheral current consumption the current consumption of the on-chip peripherals is given in the following tables. the mcu is placed under the following conditions: ? all i/o pins are in input mode with a static value at v dd or v ss (no load) ? all peripherals are disabled unless otherwise mentioned ? the given value is calculated by measuring the current consumption ? with all peripherals clocked off ? with only one peripheral clocked on table 35. typical and maximum current consumptions in standby mode symbol parameter conditions typ max (1) unit i dd (standby) supply current in standby mode independent watchdog and lsi enabled t a = -40 c to 25 c 1.3 1.7 a t a = 55 c - 2.9 t a = 85 c - 3.3 t a = 105 c - 4.1 t a = 125 c - 8.5 independent watchdog and lsi off t a = -40 c to 25 c 0.29 0.6 t a = 55 c 0.32 0.9 t a = 85 c 0.5 2.3 t a = 105 c 0.94 3 t a = 125 c 2.6 7 1. guaranteed by characterization results at 125 c, not tested in production, unless otherwise specified table 36. average current consumption during wakeup symbol parameter system frequency current consumption during wakeup unit i dd (wu from stop) supply current during wakeup from stop mode hsi 1 ma hsi/4 0,7 msi 4,2 mhz 0,7 msi 1,05 mhz 0,4 msi 65 khz 0,1 i dd (reset) reset pin pulled down - 0,21 i dd (power up) bor on - 0,23 i dd (wu from standby) with fast wakeup set msi 2,1 mhz 0,5 with fast wakeup disabled msi 2,1 mhz 0,12 docid025938 rev 4 63/119 stm32l051x6 stm32l051x8 electrical characteristics 97 table 37. peripheral current consumption in run or sleep mode (1) peripheral typical consumption, v dd = 3.0 v, t a = 25 c unit range 1, v core =1.8 v vos[1:0] = 01 range 2, v core =1.5 v vos[1:0] = 10 range 3, v core =1.2 v vos[1:0] = 11 low-power sleep and run apb1 wwdg 3 2 2 2 a/mhz (f hclk ) spi2 9 4.5 3.5 4 lpuart1 8 6.5 5.5 6 i2c1 11 9.5 7.5 9 i2c2 4 3.5 3 2.5 usart2 14.5 12 9.5 11 lptim1 10 8.5 6.5 8 tim2 10.5 8.5 7 9 tim6 3.5 3 2.5 2 crs 2.5 2 2 2 apb2 adc1 (2) 5.5 5 3.5 4 a/mhz (f hclk ) spi1 4 3 3 2.5 usart1 14.5 11.5 9.5 12 tim21 7.5 6 5 5.5 tim22 7 6 5 6 firewall 1.5 1 1 0.5 dbgmcu 1.5 1 1 0.5 syscfg 2.5 2 2 1.5 cortex- m0+ core i/o port gpioa 3.5 3 2.5 2.5 a/mhz (f hclk ) gpiob 3.5 2.5 2 2.5 gpioc 8.5 6.5 5.5 7 gpiod 1 0.5 0.5 0.5 gpioh 1.5 1 1 0.5 ahb crc 1.5 1 1 1 a/mhz (f hclk ) flash 0 (3) 0 (3) 0 (3) 0 (3) dma1 10 8 6.5 8.5 rng 5.5 1 0.5 0.5 tsc 3 2.5 2 3 all enabled 279 221.5 219.5 215 pwr 2.5 2 2 1 a/mhz (f hclk ) electrical characteristics stm32l051x6 stm32l051x8 64/119 docid025938 rev 4 6.3.5 wakeup time from low-power mode the wakeup times given in the following table are measured with the msi or hsi16 rc oscillator. the clock source us ed to wake up the device d epends on the cu rrent op erating mode: ? sleep mode: the clock source is the clock that was set before entering sleep mode ? stop mode: the clock source is either the ms i oscillator in the range configured before entering stop mode, the hsi16 or hsi16/4. ? standby mode: the clock source is the msi oscillator running at 2.1 mhz all timings are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 23 . 1. data based on differential i dd measurement between all peripheral s off an one peripheral with clock enabled, in the following conditions: f hclk = 32 mhz (range 1), f hclk = 16 mhz (range 2), f hclk = 4 mhz (range 3), f hclk = 64khz (low-power run/sleep), f apb1 = f hclk , f apb2 = f hclk , default prescaler value for each peripheral. the cpu is in sleep mode in both cases. no i/o pins toggling. not tested in production. 2. hsi oscillator is off for this measure. 3. current consumption is negligible and close to 0 a. table 38. peripheral current consumption in stop and standby mode symbol peripheral typical consumption, t a = 25 c unit v dd =1.8 v v dd =3.0 v i dd(pvd / bor) -0.71.2 a i refint --1.4 - lse low drive (1) 0,1 0,1 - lptim1, input 100 hz 0,01 0,01 - lptim1, input 1 mhz 6 6 - lpuart1 0,2 0,2 -rtc0,30,48 1. lse low drive consumption is the difference between an external clock on osc32_in and a quartz between osc32_in and osc32_out.- docid025938 rev 4 65/119 stm32l051x6 stm32l051x8 electrical characteristics 97 6.3.6 external clock source characteristics high-speed external user clock generated from an external source in bypass mode the hse oscillator is switched off and the input pin is a standard gpio.the external clock signal has to re spect the i/o characteristics in section 6.3.12 . however, the recommended clock input waveform is shown in figure 19 . table 39. low-power mode wakeup timings symbol parameter conditions typ unit t wusleep wakeup from sleep mode f hclk = 32 mhz 0.42 s t wusleep_lp wakeup from low-power sleep mode, f hclk = 262 khz f hclk = 262 khz flash enabled 4.5 f hclk = 262 khz flash switched off 7.7 t wustop wakeup from stop mode, regulator in run mode f hclk = f msi = 4.2 mhz 5.09 f hclk = f hsi = 16 mhz 4.90 f hclk = f hsi /4 = 4 mhz 7.93 wakeup from stop mode, regulator in low-power mode f hclk = f msi = 4.2 mhz voltage range 1 5.13 f hclk = f msi = 4.2 mhz voltage range 2 5.09 f hclk = f msi = 4.2 mhz voltage range 3 5.08 f hclk = f msi = 2.1 mhz 7.5 f hclk = f msi = 1.05 mhz 13.5 f hclk = f msi = 524 khz 27.6 f hclk = f msi = 262 khz 51.7 f hclk = f msi = 131 khz 102.3 f hclk = msi = 65 khz 197.2 f hclk = f hsi = 16 mhz 4.80 f hclk = f hsi /4 = 4 mhz 7.95 wakeup from stop mode, regulator in low-power mode, code running from ram f hclk = f hsi = 16 mhz 4.86 f hclk = f hsi /4 = 4 mhz 8.04 f hclk = f msi = 4.2 mhz 5.06 t wustdby wakeup from standby mode fwu bit = 1 f hclk = msi = 2.1 mhz 67.5 wakeup from standby mode fwu bit = 0 f hclk = msi = 2.1 mhz 2.56 ms electrical characteristics stm32l051x6 stm32l051x8 66/119 docid025938 rev 4 figure 19. high-speed external clock source ac timing diagram table 40. high-speed external user clock characteristics (1) 1. guaranteed by design, not tested in production. symbol parameter conditions min typ max unit f hse_ext user external clock source frequency css is on or pll is used 1832mhz css is off, pll not used 0832mhz v hseh osc_in input pin high level voltage - 0.7v dd -v dd v v hsel osc_in input pin low level voltage v ss -0.3v dd t w(hse) t w(hse) osc_in high or low time 12 - - ns t r(hse) t f(hse) osc_in rise or fall time - - 20 c in(hse) osc_in input capacitance - 2.6 - pf ducy (hse) duty cycle 45 - 55 % i l osc_in input leakage current v ss v in v dd --1a d l f 2 6 & b , 1 ( ; 7 ( 5 1 $ / 6 7 0 / [ [ & / 2 & . 6 2 8 5 & ( 9 + 6 ( + w i + 6 ( w : + 6 ( , / 7 + 6 ( w w u + 6 ( w : + 6 ( i + 6 ( b h [ w 9 + 6 ( / docid025938 rev 4 67/119 stm32l051x6 stm32l051x8 electrical characteristics 97 low-speed external user clock generated from an external source the characteristics given in the following table result from tests performed using a low- speed external clock source, and under ambien t temperature and supply voltage conditions summarized in table 23 . figure 20. low-speed external clock source ac timing diagram high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 1 to 25 mhz crystal/ceramic resonator oscillator. all th e information given in this paragraph are based on characterization results obtained with typical external components specified in table 42 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion an d startup stabilization table 41. low-speed external user clock characteristics (1) 1. guaranteed by design, not tested in production symbol parameter conditions min typ max unit f lse_ext user external clock source frequency - 1 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd -v dd v v lsel osc32_in input pin low level voltage v ss -0.3v dd t w(lse) t w(lse) osc32_in high or low time 465 - - ns t r(lse) t f(lse) osc32_in rise or fall time - - 10 c in(lse) osc32_in input capacitance - - 0.6 - pf ducy (lse) duty cycle - 45 - 55 % i l osc32_in input leakage current v ss v in v dd --1a d l f 2 6 & b , 1 ( ; 7 ( 5 1 $ / 6 7 0 / [ [ & / 2 & . 6 2 8 5 & ( 9 / 6 ( + w i / 6 ( w : / 6 ( , / 7 / 6 ( w w u / 6 ( w : / 6 ( i / 6 ( b h [ w 9 / 6 ( / electrical characteristics stm32l051x6 stm32l051x8 68/119 docid025938 rev 4 time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequenc y, package, accuracy). for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high- frequency applications, and selected to match the requirements of the crystal or resonator (see figure 21 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . refer to the application note an28 67 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. figure 21. hse oscilla tor circuit diagram low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillator. all th e information given in this paragraph are based on characterization results obtained with typical external components specified in table 43 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion an d startup stabilization table 42. hse oscillator characteristics (1) 1. guaranteed by design, not tested in production. symbol parameter conditions min typ max unit f osc_in oscillator frequency - 1 25 mhz r f feedback resistor - - 200 - k g m maximum critical crystal transconductance startup - - 700 a /v t su(hse) (2) 2. guaranteed by characterization resu lts, not tested in production. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stab ilized 8 mhz oscillation is reached. this value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. startup time v dd is stabilized - 2 - ms 2 6 & b 2 8 7 2 6 & b , 1 i + 6 ( w r f r u h & / & / 5 ) 6 7 0 5 h v r q d w r u & r q v x p s w l r q f r q w u r o j p 5 p & p / p & 2 5 h v r q d w r u d l e docid025938 rev 4 69/119 stm32l051x6 stm32l051x8 electrical characteristics 97 time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequenc y, package, accuracy). note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. figure 22. typical applicati on with a 32.768 khz crystal note: an external resistor is not required between osc32_in and osc32_out and it is forbidden to add one. table 43. lse oscillator characteristics (1) symbol parameter conditions (2) min (2) typ max unit f lse lse oscillator frequency - 32.768 - khz g m maximum critical crystal transconductance lsedrv[1:0]=00 lower driving capability --0.5 a/v lsedrv[1:0]= 01 medium low driving capability - - 0.75 lsedrv[1:0] = 10 medium high driving capability --1.7 lsedrv[1:0]=11 higher driving capability --2.7 t su(lse) (3) startup time v dd is stabilized - 2 - s 1. guaranteed by design, not tested in production. 2. refer to the note and caution paragraphs below the table, and to the application note an2867 ?oscillator design guide for st microcontrollers?. 3. guaranteed by characterization results, not tested in production. t su(lse) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 khz oscillation is reached. this value is measured for a standard crystal resonator and it can vary significantly with the crystal manuf acturer. to increase speed, address a lower-drive quartz with a high- driver mode. 0 6 9 2 6 & b 2 8 7 2 6 & b , 1 i / 6 ( & / n + ] u h v r q d w r u & / 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v ' u l y h s u r j u d p p d e o h d p s o l i l h u electrical characteristics stm32l051x6 stm32l051x8 70/119 docid025938 rev 4 6.3.7 internal clock source characteristics the parameters given in table 44 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 23 . high-speed internal 16 mhz (hsi16) rc oscillator figure 23. hsi16 minimum and maxi mum value versus temperature table 44. 16 mhz hsi16 oscillator characteristics symbol parameter conditions min typ max unit f hsi16 frequency v dd = 3.0 v - 16 - mhz trim (1)(2) 1. the trimming step differs depending on the trimming code. it is usually negativ e on the codes which are multiples of 16 (0x00, 0x10, 0x20, 0x30...0xe0). hsi16 user- trimmed resolution trimming code is not a multiple of 16 - 0.4 0.7 % trimming code is a multiple of 16 - - 1.5 % acc hsi16 (2) 2. guaranteed by characterization re sults, not tested in production. accuracy of the factory-calibrated hsi16 oscillator v dda = 3.0 v, t a = 25 c -1 (3) 3. guaranteed by test in production. -1 (3) % v dda = 3.0 v, t a = 0 to 55 c -1.5 - 1.5 % v dda = 3.0 v, t a = -10 to 70 c -2 - 2 % v dda = 3.0 v, t a = -10 to 85 c -2.5 - 2 % v dda = 3.0 v, t a = -10 to 105 c -4 - 2 % v dda = 1.65 v to 3.6 v t a = -40 to 125 c -5.45 - 3.25 % t su(hsi16) (2) hsi16 oscillator startup time - - 3.7 6 s i dd(hsi16) (2) hsi16 oscillator power consumption - - 100 140 a 0 6 y 9 9 p l q 9 w \ s 9 p d [ 9 p d [ 9 p l q docid025938 rev 4 71/119 stm32l051x6 stm32l051x8 electrical characteristics 97 low-speed internal (lsi) rc oscillator multi-speed internal (msi) rc oscillator table 45. lsi oscillator characteristics symbol parameter min typ max unit f lsi (1) 1. guaranteed by test in production. lsi frequency 26 38 56 khz d lsi (2) 2. this is a deviation for an individual part, once the init ial frequency has been measured. lsi oscillator frequency drift 0c t a 85c -10 - 4 % t su(lsi) (3) 3. guaranteed by design, not tested in production. lsi oscillator startup time - - 200 s i dd(lsi) (3) lsi oscillator power consumption - 400 510 na table 46. msi oscillator characteristics symbol parameter condition typ max unit f msi frequency after factory calibration, done at v dd = 3.3 v and t a = 25 c msi range 0 65.5 - khz msi range 1 131 - msi range 2 262 - msi range 3 524 - msi range 4 1.05 - mhz msi range 5 2.1 - msi range 6 4.2 - acc msi frequency error after factory calibration - 0.5 - % d temp(msi) (1) msi oscillator frequency drift 0 c t a 85 c - 3-% d volt(msi) (1) msi oscillator frequency drift 1.65 v v dd 3.6 v, t a = 25 c --2.5%/v i dd(msi) (2) msi oscillator power consumption msi range 0 0.75 - a msi range 1 1 - msi range 2 1.5 - msi range 3 2.5 - msi range 4 4.5 - msi range 5 8 - msi range 6 15 - electrical characteristics stm32l051x6 stm32l051x8 72/119 docid025938 rev 4 6.3.8 pll characteristics the parameters given in table 47 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 23 . t su(msi) msi oscillator startup time msi range 0 30 - s msi range 1 20 - msi range 2 15 - msi range 3 10 - msi range 4 6 - msi range 5 5 - msi range 6, voltage range 1 and 2 3.5 - msi range 6, voltage range 3 5- t stab(msi) (2) msi oscillator stabilization time msi range 0 - 40 s msi range 1 - 20 msi range 2 - 10 msi range 3 - 4 msi range 4 - 2.5 msi range 5 - 2 msi range 6, voltage range 1 and 2 -2 msi range 3, voltage range 3 -3 f over(msi) msi oscillator frequency overshoot any range to range 5 -4 mhz any range to range 6 -6 1. this is a deviation for an individual part, once the init ial frequency has been measured. 2. guaranteed by characterization results, not tested in production. table 46. msi oscillator characteristics (continued) symbol parameter condition typ max unit table 47. pll characteristics symbol parameter value unit min typ max (1) f pll_in pll input clock (2) 2- 24mhz pll input clock duty cycle 45 - 55 % docid025938 rev 4 73/119 stm32l051x6 stm32l051x8 electrical characteristics 97 6.3.9 memory characteristics ram memory f pll_out pll output clock 2 - 32 mhz t lock pll input = 16 mhz pll vco = 96 mhz - 115 160 s jitter cycle-to-cycle jitter - 600 ps i dda (pll) current consumption on v dda - 220 450 a i dd (pll) current consumption on v dd - 120 150 1. guaranteed by characterization results, not tested in production. 2. take care of using the appropriate multiplier factors so as to have pll input clock values compatible with the range defined by f pll_out . table 47. pll characteristics (continued) symbol parameter value unit min typ max (1) table 48. ram and hardware registers symbol parameter cond itions min typ max unit vrm data retention mode (1) 1. minimum supply voltage without losing data stored in ram (in stop mode or under reset) or in hardware registers (only in stop mode). stop mode (or reset) 1.65 - - v electrical characteristics stm32l051x6 stm32l051x8 74/119 docid025938 rev 4 flash memory and data eeprom table 49. flash memo ry and data eeprom characteristics symbol parameter conditions min typ max (1) 1. guaranteed by design, not tested in production. unit v dd operating voltage read / write / erase -1.65-3.6v t prog programming time for word or half-page erasing - 3.28 3.94 ms programming - 3.28 3.94 i dd average current during the whole programming / erase operation t a = 25 c, v dd = 3.6 v - 500 700 a maximum current (peak) during the whole programming / erase operation -1.52.5ma table 50. flash memory and data eeprom endurance and retention symbol parameter conditions value unit min (1) 1. guaranteed by characterization re sults, not tested in production. n cyc (2) cycling (erase / write) program memory t a = -40c to 105 c 10 kcycles cycling (erase / write) eeprom data memory 100 cycling (erase / write) program memory t a = -40c to 125 c 0.2 cycling (erase / write) eeprom data memory 2 t ret (2) 2. characterization is done according to jedec jesd22-a117. data retention (program memory) after 10 kcycles at t a = 85 c t ret = +85 c 30 years data retention (eeprom data memory) after 100 kcycles at t a = 85 c 30 data retention (program memory) after 10 kcycles at t a = 105 c t ret = +105 c 10 data retention (eeprom data memory) after 100 kcycles at t a = 105 c data retention (program memory) after 200 cycles at t a = 125 c t ret = +125 c data retention (eeprom data memory) after 2 kcycles at t a = 125 c docid025938 rev 4 75/119 stm32l051x6 stm32l051x8 electrical characteristics 97 6.3.10 emc characteristics susceptibility tests are perf ormed on a sample basis duri ng device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on t he device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure o ccurs. the failure is indicated by the leds: ? electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a func tional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in table 51 . they are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu soft ware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in re lation with the emc level requested for his application. software recommendations the software flowchart must include the m anagement of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. table 51. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, lqfp100, t a = +25 c, f hclk = 32 mhz conforms to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, lqfp100, t a = +25 c, f hclk = 32 mhz conforms to iec 61000-4-4 4a electrical characteristics stm32l051x6 stm32l051x8 76/119 docid025938 rev 4 to complete these trials, esd stress can be applie d directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 leds through the i/o por ts). this emission test is compliant with iec 61967-2 standard which specifies the test board and the pin loading. 6.3.11 electrical sens itivity characteristics based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determ ine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the ansi/jedec standard. table 52. emi characteristics symbol parameter conditions monitored frequency band max vs. frequency range unit 4 mhz voltage range 3 16 mhz voltage range 2 32 mhz voltage range 1 s emi peak level v dd = 3.3 v, t a = 25 c, lqfp100 package compliant with iec 61967-2 0.1 to 30 mhz 3 -6 -5 dbv 30 to 130 mhz 18 4 -7 130 mhz to 1ghz 15 5 -7 sae emi level 2.5 2 1 - table 53. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. guaranteed by characterization re sults, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c, conforming to ansi/jedec js-001 22000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c, conforming to ansi/esd stm5.3.1. c4 500 docid025938 rev 4 77/119 stm32l051x6 stm32l051x8 electrical characteristics 97 static latch-up two complementary static te sts are required on six pa rts to assess the latch-up performance: ? a supply overvoltage is applied to each power supply pin ? a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78a ic latch-up standard. 6.3.12 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard pins) should be avoided during normal product operation. however, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection acci dentally happens, susceptibility tests are performed on a sample basis during device characterization. functional susceptibility to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode . while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (higher than 5 lsb tue), out of conventional limits of induced leakage current on adjacent pins (out of ?5 a/+0 a range), or ot her functional failure (for ex ample reset occurrence oscillator frequency deviation). the test results are given in the table 55 . table 54. electrical sensitivities symbol parameter conditions class lu static latch-up class t a = +125 c conforming to jesd78a ii level a table 55. i/o current injection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj injected current on boot0 -0 na ma injected current on all ft pins -5 (1) 1. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. na injected current on any other pin -5 (1) +5 electrical characteristics stm32l051x6 stm32l051x8 78/119 docid025938 rev 4 6.3.13 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in table 56 are derived from tests performed under the conditions summarized in table 23 . all i/os are cmos and ttl compliant. table 56. i/o static characteristics symbol parameter conditions min typ max unit v il input low level voltage tc, ft, ftf, rst i/os - - 0.3v dd v boot0 pin - - 0.14v dd (1) v ih input high level vo ltage all i/os 0.7 v dd -- v hys i/o schmitt trigger voltage hysteresis (2) standard i/os - 10% v dd (3) - boot0 pin - 0.01 - i lkg input leakage current (4) v ss v in v dd i/os with analog switches --50 na v ss v in v dd standard i/os --50 ft i/o v dd v in 5 v --10a r pu weak pull-up equivalent resistor (5) v in = v ss 30 45 60 k r pd weak pull-down equivalent resistor (5) v in = v dd 30 45 60 k c io i/o pin capacitance - - 5 - pf 1. g uaranteed by characterization, not tested in production 2. hysteresis voltage between schmitt trigger switching levels. guaranteed by characteri zation results, not tested in production . 3. with a minimum of 200 mv. guaranteed by c haracterization results, not tested in production. 4. the max. value may be exceeded if negative current is injected on adjacent pins. 5. pull-up and pull-down resistor s are designed with a true resistance in seri es with a switchable pmos/nmos. this mos/nmos contribution to the series resistance is minimum (~10% order). docid025938 rev 4 79/119 stm32l051x6 stm32l051x8 electrical characteristics 97 figure 24. v ih /v il versus vdd (cmos i/os) figure 25. v ih /v il versus vdd (ttl i/os) output driving current the gpios (general purpose input/outputs) can si nk or source up to 8 ma, and sink or source up to 15 ma with the non-standard v ol /v oh specifications given in table 57 . in the user application, the number of i/o pi ns which can drive curr ent must be limited to respect the absolute maximum rating specified in section 6.2 : ? the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd( ) (see table 21 ). ? the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss( ) (see table 21 ). 0 6 y 9 9 ' ' 9 9 , + p l q 9 , / p d [ 9 , / 9 , + 9 & 0 2 6 v w d q g d u g u h t x l u h p h q w v 9 , + p l q 9 ' ' 9 , / p d [ 9 ' ' & 0 2 6 v w d q g d u g u h t x l u h p h q w v 9 , / p d [ 9 ' ' 9 , + p l q 9 ' ' d o o s l q v h [ f h s w % 2 2 7 3 & 3 + 9 , + p l q 9 ' ' i r u % 2 2 7 3 & 3 + , q s x w u d q j h q r w j x d u d q w h h g 0 6 y 9 9 ' ' 9 9 , + p l q 9 , / p d [ 9 , / 9 , + 9 7 7 / v w d q g d u g u h t x l u h p h q w v 9 , + p l q 9 9 , / p d [ 9 ' ' 7 7 / v w d q g d u g u h t x l u h p h q w v 9 , / p d [ 9 , q s x w u d q j h q r w j x d u d q w h h g 9 , + p l q 9 ' ' d o o s l q v h [ f h s w % 2 2 7 3 & 3 + 9 , + p l q 9 ' ' i r u % 2 2 7 3 & 3 + electrical characteristics stm32l051x6 stm32l051x8 80/119 docid025938 rev 4 output voltage levels unless otherwise specified, the parameters given in table 57 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 23 . all i/os are cmos and ttl compliant. table 57. output voltage characteristics symbol parameter conditions min max unit v ol (1) 1. the i io current sunk by the device must always respect the absolute maximum rating specified in table 21 . the sum of the currents sunk by all the i/os (i/o ports and control pins) must always be respected and must not exceed i io(pin) . output low level voltage for an i/o pin cmos port (2) , i io = +8 ma 2.7 v v dd 3.6 v 2. ttl and cmos outputs are compatible with jedec standards jesd36 and jesd52. -0.4 v v oh (3) 3. the i io current sourced by the device must always re spect the absolute maximum rating specified in table 21 . the sum of the currents sourced by all the i/o s (i/o ports and control pins) must always be respected and must not exceed i io(pin) . output high level voltage for an i/o pin v dd -0.4 - v ol (1) output low level voltage for an i/o pin ttl port (2) , i io =+ 8 ma 2.7 v v dd 3.6 v -0.4 v oh (3)(4) 4. guaranteed by characterization results, not tested in production. output high level voltage for an i/o pin ttl port (2) , i io = -6 ma 2.7 v v dd 3.6 v 2.4 - v ol (1)(4) output low level voltage for an i/o pin i io = +15 ma 2.7 v v dd 3.6 v -1.3 v oh (3)(4) output high level voltage for an i/o pin i io = -15 ma 2.7 v v dd 3.6 v v dd -1.3 - v ol (1)(4) output low level voltage for an i/o pin i io = +4 ma 1.65 v v dd < 3.6 v -0.45 v oh (3)(4) output high level voltage for an i/o pin i io = -4 ma 1.65 v v dd 3.6 v v dd -0.45 - v olfm+ (1)(4) output low level voltage for an ftf i/o pin in fm+ mode i io = 20 ma 2.7 v v dd 3.6 v -0.4 i io = 10 ma 1.65 v v dd 3.6 v -0.4 docid025938 rev 4 81/119 stm32l051x6 stm32l051x8 electrical characteristics 97 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 26 and table 58 , respectively. unless otherwise specified, the parameters given in table 58 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 23 . table 58. i/o ac characteristics (1) ospeedrx [1:0] bit value (1) symbol parameter conditions min max (2) unit 00 f max(io)out maximum frequency (3) c l = 50 pf, v dd = 2.7 v to 3.6 v - 400 khz c l = 50 pf, v dd = 1.65 v to 2.7 v - 100 t f(io)out t r(io)out output rise and fall time c l = 50 pf, v dd = 2.7 v to 3.6 v - 125 ns c l = 50 pf, v dd = 1.65 v to 2.7 v - 320 01 f max(io)out maximum frequency (3) c l = 50 pf, v dd = 2.7 v to 3.6 v - 2 mhz c l = 50 pf, v dd = 1.65 v to 2.7 v - 0.6 t f(io)out t r(io)out output rise and fall time c l = 50 pf, v dd = 2.7 v to 3.6 v - 30 ns c l = 50 pf, v dd = 1.65 v to 2.7 v - 65 10 f max(io)out maximum frequency (3) c l = 50 pf, v dd = 2.7 v to 3.6 v - 10 mhz c l = 50 pf, v dd = 1.65 v to 2.7 v - 2 t f(io)out t r(io)out output rise and fall time c l = 50 pf, v dd = 2.7 v to 3.6 v - 13 ns c l = 50 pf, v dd = 1.65 v to 2.7 v - 28 11 f max(io)out maximum frequency (3) c l = 30 pf, v dd = 2.7 v to 3.6 v - 35 mhz c l = 50 pf, v dd = 1.65 v to 2.7 v - 10 t f(io)out t r(io)out output rise and fall time c l = 30 pf, v dd = 2.7 v to 3.6 v - 6 ns c l = 50 pf, v dd = 1.65 v to 2.7 v - 17 -t extipw pulse width of external signals detected by the exti controller -8-ns 1. the i/o speed is configured using the ospeedrx[1:0] bits. refer to the line reference m anual for a description of gpio port configuration register. 2. guaranteed by design. not tested in production. 3. the maximum frequency is defined in figure 26 . electrical characteristics stm32l051x6 stm32l051x8 82/119 docid025938 rev 4 figure 26. i/o ac charac teristics definition 6.3.14 nrst pin characteristics the nrst pin input driver uses cmos technology. it is connected to a permanent pull-up resistor, r pu , except when it is internally driven low (see table 59 ). unless otherwise specified, the parameters given in table 59 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 23 . d l g w u , 2 r x w 2 8 7 3 8 7 ( ; 7 ( 5 1 $ / 2 1 & / 0 d [ l p x p i u h t x h q f \ l v d f k l h y h g l i w u w i ? 7 d q g l i w k h g x w \ f \ f o h l v z k h q o r d g h g e \ & / v s h f l i l h g l q w k h w d e o h 3 , 2 $ & f k d u d f w h u l v w l f v 7 w i , 2 r x w table 59. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) (1) 1. guaranteed by design, not tested in production. nrst input low level voltage - v ss -0.8 v v ih(nrst) (1) nrst input high level voltage - 1.4 - v dd v ol(nrst) (1) nrst output low level voltage i ol = 2 ma 2.7 v < v dd < 3.6 v -- 0.4 i ol = 1.5 ma 1.65 v < v dd < 2.7 v -- v hys(nrst) (1) nrst schmitt trigger voltage hysteresis --10%v dd (2) 2. 200 mv minimum value -mv r pu weak pull-up equivalent resistor (3) 3. the pull-up is designed with a true resistance in series with a switchable pmos. this pmos contribution to the series resistance is around 10%. v in = v ss 30 45 60 k v f(nrst) (1) nrst input filtered pulse - - - 50 ns v nf(nrst) (1) nrst input not filtered pulse - 350 - - ns docid025938 rev 4 83/119 stm32l051x6 stm32l051x8 electrical characteristics 97 figure 27. recommended nrst pin protection 1. the reset network protects t he device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 59 . otherwise the reset will not be taken into account by the device. 6.3.15 12-bit adc characteristics unless otherwise specified, the parameters given in table 60 are preliminary values derived from tests performed under ambient temperature, f pclk frequency and v dda supply voltage conditions su mmarized in table 23: general operating conditions . note: it is recommended to perform a calibration after each power-up. d l f 6 7 0 / [ [ 5 3 8 1 5 6 7 9 ' ' ) l o w h u , q w h u q d o u h v h w ? ) ( [ w h u q d o u h v h w f l u f x l w table 60. adc characteristics symbol parameter conditions min typ max unit v dda analog supply voltage for adc on 1.65 - 3.6 v i dda (adc) current consumption of the adc on v dda and v ref+ 1.14 msps - 200 - a 10 ksps - 40 - current consumption of the adc on v dd (1) 1.14 msps - 70 - 10 ksps - 1 - f adc adc clock frequency voltage scaling range 1 0.14 - 16 mhz voltage scaling range 2 0.14 - 8 voltage scaling range 3 0.14 - 4 f s (2) sampling rate 0.05 - 1.14 mhz f trig (2) external trigger frequency f adc = 16 mhz - - 941 khz --171/f adc v ain conversion voltage range 0 - v dda v r ain (2) external input impedance see equation 1 and table 61 for details --50k r adc (2) sampling switch resistance - - 1 k c adc (2) internal sample and hold capacitor --8pf electrical characteristics stm32l051x6 stm32l051x8 84/119 docid025938 rev 4 equation 1: r ain max formula the formula above ( equation 1 ) is used to dete rmine the maximum external impedance allowed for an error below 1/4 of lsb. here n = 12 (from 12-bit resolution). t cal (2) calibration time f adc = 16 mhz 5.2 s 83 1/f adc w latency adc_dr register write latency adc clock = hsi16 1.5 adc cycles + 2 f pclk cycles - 1.5 adc cycles + 3 f pclk cycles - adc clock = pclk/2 - 4.5 - f pclk cycle adc clock = pclk/4 - 8.5 - f pclk cycle t latr (2) trigger conversion latency f adc = f pclk /2 = 16 mhz 0.266 s f adc = f pclk /2 8.5 1/f pclk f adc = f pclk /4 = 8 mhz 0.516 s f adc = f pclk /4 16.5 1/f pclk f adc = f hsi16 = 16 mhz 0.252 - 0.260 s jitter adc adc jitter on trigger conversion f adc = f hsi16 -1-1/f hsi16 t s (2) sampling time f adc = 16 mhz 0.093 - 15 s 1.5 - 239.5 1/f adc t stab (2) power-up time 0 0 1 s t conv (2) total conversion time (including sampling time) f adc = 16 mhz 1 15.75 s 14 to 252 (t s for sampling +12.5 for successive approximation) 1/f adc 1. a current consumption proportional to the apb clock frequency has to be added (see table 37: peripheral current consumption in run or sleep mode ). 2. guaranteed by design, not tested in production. table 60. adc characteristics (continued) symbol parameter conditions min typ max unit r ain t s f adc c adc 2 n2 + () ln ------------------------------------------------------------- - r adc ? < docid025938 rev 4 85/119 stm32l051x6 stm32l051x8 electrical characteristics 97 table 61. r ain max for f adc = 14 mhz t s (cycles) t s (s) r ain max (k ) (1) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 71.5 5.11 na 239.5 17.1 na 1. guaranteed by design, not tested in production. table 62. adc accuracy (1)(2)(3) symbol parameter conditions min typ max unit et total unadjusted error 1.65 v < v dda = v ref+ < 3.6 v, range 1/2/3 -2 4 lsb eo offset error - 1 2.5 eg gain error - 1 2 el integral linearity error - 1.5 2.5 ed differential linearity error - 1 1.5 enob effective number of bits 10.2 11 bits effective number of bits (16-bit mode oversampling with ratio =256) (4) 11.3 12.1 - sinad signal-to-noise distortion 63 69 - db snr signal-to-noise ratio 63 69 - signal-to-noise ratio (16-bit mode oversampling with ratio =256) (4) 70 76 - thd total harmonic distortion - -85 -73 et total unadjusted error 1.65 v < v ref+ < v dda < 3.6 v, range 1/2/3 -2 5 lsb eo offset error - 1 2.5 eg gain error - 1 2 el integral linearity error - 1.5 3 ed differential linearity error - 1 2 enob effective number of bits 10.0 11.0 - bits sinad signal-to-noise distortion 62 69 - db snr signal-to-noise ratio 61 69 - thd total harmonic distortion - -85 -65 1. adc dc accuracy values are meas ured after internal calibration. electrical characteristics stm32l051x6 stm32l051x8 86/119 docid025938 rev 4 figure 28. adc accuracy characteristics figure 29. typical connecti on diagram using the adc 1. refer to table 60: adc characteristics for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. 2. adc accuracy vs. negative injection current: injecting negativ e current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the ac curacy of the conversion bei ng performed on another analog input. it is recommended to add a schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. any positive injection current within the limits specified for i inj(pin) and i inj(pin) in section 6.3.12 does not affect the adc accuracy. 3. better performance may be achieved in restricted v dda , frequency and temperature ranges. 4. this number is obtained by the test boar d without additional noise, resulting in non-optimized value for oversampling mode. ( 2 ( * / 6 % , ' ( $ / ( [ d p s o h r i d q d f w x d o w u d q v i h u f x u y h 7 k h l g h d o w u d q v i h u f x u y h ( q g s r l q w f r u u h o d w l r q o l q h ( 7 7 r w d o 8 q d g m x v w h g ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q w k h d f w x d o d q g w k h l g h d o w u d q v i h u f x u y h v ( 2 2 i i v h w ( u u r u g h y l d w l r q e h w z h h q w k h i l u v w d f w x d o w u d q v l w l r q d q g w k h i l u v w l g h d o r q h ( * * d l q ( u u r u g h y l d w l r q e h w z h h q w k h o d v w l g h d o w u d q v l w l r q d q g w k h o d v w d f w x d o r q h ( ' ' l i i h u h q w l d o / l q h d u l w \ ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q d f w x d o v w h s v d q g w k h l g h d o r q h ( / , q w h j u d o / l q h d u l w \ ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q d q \ d f w x d o w u d q v l w l r q d q g w k h h q g s r l q w f r u u h o d w l r q o l q h ( 7 ( ' ( / 9 ' ' $ 9 6 6 $ - 3 6 0 6 y 9 9 ' ' $ $ , 1 [ , / ? q $ 9 7 5 $ , 1 & s d u d v l w l f 9 $ , 1 9 7 5 $ ' & e l w f r q y h u w h u & $ ' & 6 d p s o h d q g k r o g $ ' & f r q y h u w h u docid025938 rev 4 87/119 stm32l051x6 stm32l051x8 electrical characteristics 97 general pcb design guidelines power supply decoupling should be performed as shown in figure 30 or figure 31 , depending on whether v ref+ is connected to v dda or not. the 10 nf capacitors should be ceramic (good quality). they should be placed as close as possible to the chip. figure 30. power supply and reference decoupling (v ref+ not connected to v dda ) figure 31. power supply and reference decoupling (v ref+ connected to v dda ) d l e 9 5 ( ) v h h q r w h 6 7 0 / [ [ 9 ' ' $ 9 6 6 $ 9 5 ( ) v h h q r w h ? ) q ) ? ) q ) d l d 6 2 % & 6 $ $ ! 6 7 0 / [ [ ? & n & 6 2 % & n 6 3 3 ! 3 e e n o t e 3 e e n o t e electrical characteristics stm32l051x6 stm32l051x8 88/119 docid025938 rev 4 6.3.16 temperature sensor characteristics 6.3.17 comparators table 63. temperature sensor calibration values calibration value name description memory address ts_cal1 ts adc raw data acquired at temperature of 30 c, v dda = 3 v 0x1ff8 007a - 0x1ff8 007b ts_cal2 ts adc raw data acquired at temperature of 130 c v dda = 3 v 0x1ff8 007e - 0x1ff8 007f table 64. temperature sensor characteristics symbol parameter min typ max unit t l (1) 1. guaranteed by characterization results, not tested in production. v sense linearity with temperature - 1 2c avg_slope (1) average slope 1.48 1.61 1.75 mv/c v 130 voltage at 130c 5c (2) 2. measured at v dd = 3 v 10 mv. v130 adc conversion result is stored in the ts_cal2 byte. 640 670 700 mv i dda (temp) (3) current consumption - 3.4 6 a t start (3) 3. guaranteed by design, not tested in production. startup time - - 10 s t s_temp (4)(3) 4. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the temperature 10 - - table 65. comparator 1 characteristics symbol parameter conditions min (1) typ max (1) unit v dda analog supply voltage - 1.65 3.6 v r 400k r 400k value - - 400 - k r 10k r 10k value - - 10 - v in comparator 1 input voltage range -0.6-v dda v t start comparator startup time - - 7 10 s td propagation delay (2) --310 voffset comparator offset - - 3 10 mv docid025938 rev 4 89/119 stm32l051x6 stm32l051x8 electrical characteristics 97 6.3.18 timer characteristics tim timer characteristics the parameters given in the table 67 are guaranteed by design. refer to section 6.3.13: i/o port characteristics for details on the input/output alternate function characteristics (output compare, i nput capture, external clock, pwm output). d voffset /dt comparator offset variation in worst voltage stress conditions v dda = 3.6 v v in+ = 0 v v in- = v refint t a = 25 c 0 1.5 10 mv/1000 h i comp1 current consumption (3) - - 160 260 na 1. guaranteed by characterization, not tested in production. 2. the delay is characterized for 100 mv input step wi th 10 mv overdrive on the inverting input, the non- inverting input set to the reference. 3. comparator consumption only. internal reference voltage not included. table 66. comparator 2 characteristics symbol parameter conditions min typ max (1) 1. guaranteed by characterization results, not tested in production. unit v dda analog supply voltage - 1.65 - 3.6 v v in comparator 2 input voltage range - 0 - v dda v t start comparator startup time fast mode - 15 20 s slow mode - 20 25 t d slow propagation delay (2) in slow mode 2. the delay is characterized for 100 mv input step with 10 mv overdrive on the inverting input, the non- inverting input set to the reference. 1.65 v v dda 2.7 v - 1.8 3.5 2.7 v v dda 3.6 v - 2.5 6 t d fast propagation delay (2) in fast mode 1.65 v v dda 2.7 v - 0.8 2 2.7 v v dda 3.6 v - 1.2 4 v offset comparator offset error - 4 20 mv dthreshold/ dt threshold voltage temperature coefficient v dda = 3.3v t a = 0 to 50 c v- =v refint , 3/4 v refint , 1/2 v refint , 1/4 v refint . -15 30 ppm /c i comp2 current consumption (3) 3. comparator consumption only. internal reference voltage (necessary for comparator operation) is not included. fast mode - 3.5 5 a slow mode - 0.5 2 table 65. comparator 1 characteristics (continued) symbol parameter conditions min (1) typ max (1) unit electrical characteristics stm32l051x6 stm32l051x8 90/119 docid025938 rev 4 table 67. timx (1) characteristics 1. timx is used as a general term to refer to the tim2, tim6, tim21, and tim22 timers. symbol parameter conditions min max unit t res(tim) timer resolution time 1-t timxclk f timxclk = 32 mhz 31.25 - ns f ext timer external clock frequency on ch1 to ch4 0f timxclk /2 mhz f timxclk = 32 mhz 0 16 mhz res tim timer resolution - 16 bit t counter 16-bit counter clock period when internal clock is selected (timer?s prescaler disabled) - 1 65536 t timxclk f timxclk = 32 mhz 0.0312 2048 s t max_count maximum possible count - - 65536 65536 t timxclk f timxclk = 32 mhz - 134.2 s docid025938 rev 4 91/119 stm32l051x6 stm32l051x8 electrical characteristics 97 6.3.19 communications interfaces i 2 c interface characteristics the i 2 c interface meets the timings requirements of the i 2 c-bus specification and user manual rev. 03 for: ? standard-mode (sm) : with a bit rate up to 100 kbit/s ? fast-mode (fm) : with a bit rate up to 400 kbit/s ? fast-mode plus (fm+) : with a bit rate up to 1 mbit/s. the i 2 c timing requirements are guaranteed by design when the i 2 c peripheral is properly configured (refer to the reference manual for details). the sda and scl i/o requirements are met with the following restrictions: the sda and scl i/o pins are not "true" open-drain. when configured as open-drain, the pmos c onnected between the i/ o pin and vddiox is disabled, but is still present. only ftf i/o pins support fm+ low level output current maximum requirement (refer to section 6.3.13: i/o port characteristics for the i2c i/os characteristics). all i 2 c sda and scl i/os embed an analog filter (see table 68 for the analog filter characteristics). table 68. i2c analog filter characteristics (1) 1. guaranteed by design, not tested in production. symbol parameter min max unit t af maximum pulse width of spikes that are suppressed by the analog filter 50 (2) 2. spikes with widths below t af(min) are filtered. 260 (3) 3. spikes with widths above t af(max) are not filtered ns electrical characteristics stm32l051x6 stm32l051x8 92/119 docid025938 rev 4 spi characteristics unless otherwise specified, th e parameters given in the following tables are derived from tests performed under ambient temperature, f pclkx frequency and v dd supply voltage conditions su mmarized in table 23 . refer to section 6.3.12: i/o current injection char acteristics for more details on the input/output alternate function char acteristics (nss, sck, mosi, miso). table 69. spi characteristics in voltage range 1 (1) symbol parameter cond itions min typ max unit f sck 1/t c(sck) spi clock frequency master mode -- 16 mhz slave mode receiver 16 slave mode transmitter 1.71 docid025938 rev 4 95/119 stm32l051x6 stm32l051x8 electrical characteristics 97 figure 33. spi timing diagram - slave mode and cpha = 1 (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd. figure 34. spi timing diagram - master mode (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd. ai14135 sck input cpha=1 mosi input miso out p ut cpha=1 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input ai14136 sck input cpha= 0 mosi output miso inp ut cpha= 0 ms bin m sb out bi t6 in lsb out lsb in cpol=0 cpol=1 b i t1 out nss input t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t h(mi) high sck input cpha=1 cpha=1 cpol=0 cpol=1 t su(mi) t v(mo) t h(mo) electrical characteristics stm32l051x6 stm32l051x8 96/119 docid025938 rev 4 i2s characteristics note: refer to the i2s section of the product refe rence manual for more details about the sampling frequency (fs), f mck , f ck and d ck values. these values reflect only the digital peripheral behavior, source clock precision might slig htly change them. dck depends mainly on the odd bit value, digital contribution leads to a min of (i2sdiv/(2*i2sdiv+odd) and a max of (i2sdiv+odd)/(2*i2sdiv+odd). fs max is supported for each mode/condition. table 72. i2s characteristics (1) symbol parameter conditions min max unit f mck i2s main clock output - 256 x 8k 256xfs (2) mhz f ck i2s clock frequency master data: 32 bits - 64xfs mhz slave data: 32 bits - 64xfs d ck i2s clock frequency duty cycle slave receiver 30 70 % t v(ws) ws valid time master mode - 15 ns t h(ws) ws hold time master mode 11 - t su(ws) ws setup time slave mode 6 - t h(ws) ws hold time slave mode 2 - t su(sd_mr) data input setup time master receiver 18 - t su(sd_sr) slave receiver 16 - t h(sd_mr) data input hold time master receiver 11 - t h(sd_sr) slave receiver 0 - t v(sd_st) data output valid time slave transmitter (after enable edge) - 77 t v(sd_mt) master transmitter (after enable edge) - 26 t h(sd_st) data output hold time slave transmitter (after enable edge) 8 - t h(sd_mt) master transmitter (after enable edge) 3 - 1. guaranteed by characterization results, not tested in production. 2. 256xfs maximum value is equal to the maximum clock frequency. docid025938 rev 4 97/119 stm32l051x6 stm32l051x8 electrical characteristics 97 figure 35. i 2 s slave timing diagram (philips protocol) (1) 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd . 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. figure 36. i 2 s master timing diagram (philips protocol) (1) 1. guaranteed by characterization results, not tested in production. 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. ck inp u t cpol = 0 cpol = 1 t c(ck) w s inp u t s d tr a n s mit s d receive t w(ckh) t w(ckl) t su (w s ) t v( s d_ s t) t h( s d_ s t) t h(w s ) t su ( s d_ s r) t h( s d_ s r) m s b receive bitn receive l s b receive m s b tr a n s mit bitn tr a n s mit l s b tr a n s mit a i14881 b l s b receive (2) l s b tr a n s mit (2) ck o u tp u t cpol = 0 cpol = 1 t c(ck) w s o u tp u t s d receive s d tr a n s mit t w(ckh) t w(ckl) t su ( s d_mr) t v( s d_mt) t h( s d_mt) t h(w s ) t h( s d_mr) m s b receive bitn receive l s b receive m s b tr a n s mit bitn tr a n s mit l s b tr a n s mit a i14884 b t f(ck) t r(ck) t v(w s ) l s b receive (2) l s b tr a n s mit (2) package characteristics stm32l051x6 stm32l051x8 98/119 docid025938 rev 4 7 package characteristics 7.1 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at http://www.st.com. ecopack ? is an st trademark. 7.1.1 lqfp32 7 x 7 mm low profile quad flat package figure 37. lqfp32, 7 x 7 mm, 32-pin low-profile quad flat package outline 1. drawing is not to scale. $ $ $ % % % ! , , + ! ! ! c b ' ! 5 ' % 0 , ! . % m m 3 % ! 4 ) . ' 0 , ! . % # 0 ) . ) $ % . 4 ) & ) # ! 4 ) / . c c c # 7 @ . & @ 7 e docid025938 rev 4 99/119 stm32l051x6 stm32l051x8 package characteristics 115 figure 38. lqfp32 recommended footprint 1. dimensions are expr essed in millimeters. table 73. lqfp32, 7 x 7 mm, 32-pin low-profile quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 - 0.200 0.0035 - 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 - 5.600 - - 0.2205 - e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 - 5.600 - - 0.2205 - e - 0.800 - - 0.0315 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - ccc - - 0.100 - - 0.0039 a - - 1.600 - - 0.0630 6 ? & 0 ? 6 package characteristics stm32l051x6 stm32l051x8 100/119 docid025938 rev 4 device marking figure 39. lqfp32 marking (package top view) 1. samples marked "es" are to be considered as "engin eering samples": i.e. they are intended to be sent to customer for electrical compatib ility evaluation and may be used to start customer qualification where specifically authorized by st in wr iting. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials. ( 6 0 6 9 ( q j l q h h u l q j v d p s o h p d u n l q j $ g g l w l r q d o l q i r u p d w l r q i l h o g l q f o x g l q j u h y l v l r q f r g h ' d w h f r g h < h d u z h h n < h d u : h h n 3 l q docid025938 rev 4 101/119 stm32l051x6 stm32l051x8 package characteristics 115 7.1.2 ufqfpn32 5 x 5 mm package figure 40. ufqfpn32, 5 x 5 mm, 32-pin package outline 1. drawing is not to scale. ! " ? - % ? 6 package characteristics stm32l051x6 stm32l051x8 102/119 docid025938 rev 4 figure 41. ufqfpn32 recommended footprint 1. dimensions are expr essed in millimeters. table 74. ufqfpn32, 5 x 5 mm, 32-pin package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.500 0.550 0.600 0.0197 0.0217 0.0236 a1 0.000 0.020 0.050 0.0000 0.0008 0.0020 a3 - 0.200 - - 0.0079 - b 0.180 0.250 0.300 0.0071 0.0098 0.0118 d 4.900 5.000 5.100 0.1929 0.1969 0.2008 d2 3.200 3.450 3.700 0.1260 0.1358 0.1457 e 4.900 5.000 5.100 0.1929 0.1969 0.2008 e2 3.200 3.450 3.700 0.1260 0.1358 0.1457 e - 0.500 - - 0.0197 - l 0.300 0.400 0.500 0.0118 0.0157 0.0197 ddd - - 0.080 - - 0.0031 $ % b ) 3 b 9 docid025938 rev 4 103/119 stm32l051x6 stm32l051x8 package characteristics 115 device marking figure 42. ufqfpn32 marking (package top view) 1. samples marked "e" are to be consid ered as "engineering samples": i.e. they are intended to be sent to customer for electrical compatib ility evaluation and may be used to start customer qualification where specifically authorized by st in wr iting. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials. ( 0 6 9 ( q j l q h h u l q j v d p s o h p d u n l q j $ g g l w l r q d o l q i r u p d w l r q i l h o g l q f o x g l q j u h y l v l r q f r g h ' d w h f r g h < h d u z h h n < h d u : h h n package characteristics stm32l051x6 stm32l051x8 104/119 docid025938 rev 4 7.1.3 lqfp48 7 x 7 mm low profile quad flat package figure 43. lqfp48, 7 x 7 mm, 48-pin low-profile quad flat package outline 1. drawing is not to scale. " ? - % ? 6 0 ) . ) $ % . 4 ) & ) # ! 4 ) / . c c c # # $ m m ' ! 5 ' % 0 , ! . % b ! ! ! c ! , , $ $ % % % e 3 % ! 4 ) . ' 0 , ! . % + docid025938 rev 4 105/119 stm32l051x6 stm32l051x8 package characteristics 115 table 75. lqfp48, 7 x 7 mm, 48-pin low-pr ofile quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 - 5.500 - - 0.2165 - e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 03.57 03.57 ccc - - 0.080 - - 0.0031 package characteristics stm32l051x6 stm32l051x8 106/119 docid025938 rev 4 figure 44. lqfp48 recommended footprint 1. dimensions are expr essed in millimeters. device marking figure 45. lqfp48 marking (package top view) 1. samples marked "es" are to be considered as "engin eering samples": i.e. they are intended to be sent to customer for electrical compatib ility evaluation and may be used to start customer qualification where specifically authorized by st in wr iting. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials. a i d ( 6 0 6 y 9 ( q j l q h h u l q j v d p s o h p d u n l q j $ g g l w l r q d o l q i r u p d w l r q i l h o g l q f o x g l q j u h y l v l r q f r g h ' d w h f r g h < h d u z h h n < h d u : h h n 3 l q docid025938 rev 4 107/119 stm32l051x6 stm32l051x8 package characteristics 115 7.1.4 lqfp64 10 x 10 mm low profile quad flat package figure 46. lqfp64, 10 x 10 mm, 64-pin low-profile quad flat package outline 1. drawing is not to scale. : b 0 ( b 9 $ $ $ 6 ( $ 7 , 1 * 3 / $ 1 ( f f f & e & f $ / / . , ' ( 1 7 , ) , & $ 7 , 2 1 3 , 1 ' ' ' h ( ( ( * $ 8 * ( 3 / $ 1 ( p p package characteristics stm32l051x6 stm32l051x8 108/119 docid025938 rev 4 figure 47. lqfp64 recommended footprint 1. dimensions are expressed in millimeters table 76. lqfp64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 11.800 12.000 12.200 0.4646 0.4724 0.4803 d1 9.800 10.000 10.200 0.3858 0.3937 0.4016 d3 - 7.500 - - 0.2953 - e 11.800 12.000 12.200 0.4646 0.4724 0.4803 e1 9.800 10.000 10.200 0.3858 0.3937 0.4016 e3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 k 0.0 3.5 7.0 0.0 3.5 7.0 docid025938 rev 4 109/119 stm32l051x6 stm32l051x8 package characteristics 115 device marking figure 48. lqfp64 marking (package top view) 1. samples marked "es" are to be considered as "engin eering samples": i.e. they are intended to be sent to customer for electrical compatib ility evaluation and may be used to start customer qualification where specifically authorized by st in wr iting. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials. 0 6 9 $ g g l w l r q d o l q i r u p d w l r q i l h o g l q f o x g l q j u h y l v l r q f r g h ( 6 ( q j l q h h u l q j v d p s o h p d u n l q j ' d w h f r g h < h d u z h h n < h d u : h h n package characteristics stm32l051x6 stm32l051x8 110/119 docid025938 rev 4 7.1.5 wlcsp36 0.4 mm pitch wa fer-level chip scale package figure 49. wlcsp36 0.4 mm pitch wafer-level chip scale package outline 1. drawing is not to scale. table 77. wlcsp36 0.4 mm pitch wafer-level chip scale package mechanical data symbol millimeters inches (1) min typ max min typ max a 0.525 0.555 0.585 0.0207 0.0219 0.0230 a1 - 0.175 - - 0.0069 - a2 - 0.380 - - 0.0150 - a3 (2) - 0.025 - - 0.0010 - b 0.220 0.250 0.280 0.0087 0.0098 0.0110 d 2.561 2.596 2.631 0.1008 0.1022 0.1036 e 2.833 2.868 2.903 0.1115 0.1129 0.1143 e - 0.400 - - 0.0157 - e1 - 2.000 - - 0.0787 - e2 - 2.000 - - 0.0787 - f - 0.298 - - 0.0117 - $ r u l h q w d w l r q u h i h u h q f h : d i h u e d f n v l g h ' h w d l o $ u r w d w h g ? 6 h d w l q j s o d q h $ % x p s e 6 l g h y l h z $ $ ' h w d l o $ h ) * h h $ e d o o o r f d w l r q h % x p s v l g h h h h = $ < b 0 ( b 9 ) $ $ = ; < = f f f g g g ? e e d o o v = d d d [ docid025938 rev 4 111/119 stm32l051x6 stm32l051x8 package characteristics 115 7.1.6 tfbga64 5 x 5 mm thin profile fi ne pitch ball grid array package figure 50. tfbga64, 5 x 5 mm, 64-bump thin profile fine pitch ball grid array package outline 1. drawing is not to scale. g - 0.434 - - 0.0171 - aaa - 0.100 - - 0.0039 - bbb - 0.100 - - 0.0039 - ccc - 0.100 - - 0.0039 - ddd - 0.050 - - 0.0020 - eee - 0.050 - - 0.0020 - 1. values in inches are converted from mm and rounded to 4 decimal digits. 2. back side coating table 77. wlcsp36 0.4 mm pitch wafer-level chip scale package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max 5 b 0 ( b 9 6 h d w l q j s o d q h $ h ) ) ' + ? e e d o o v $ ( 7 2 3 9 , ( : % 2 7 7 2 0 9 , ( : h $ < ; = g g g = ' ( h h h = < ; i i i ? ? 0 0 = $ $ $ e d o o l g h q w l i l h u $ e d o o l q g h [ d u h d package characteristics stm32l051x6 stm32l051x8 112/119 docid025938 rev 4 device marking figure 51. tfbga64 marking (package top view) 1. samples marked "es" are to be considered as "engin eering samples": i.e. they are intended to be sent to customer for electrical compatib ility evaluation and may be used to start customer qualification where specifically authorized by st in wr iting. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials. table 78. tfbga64, 5 x 5 mm, 64-bump thin profile fine pitch ball grid array package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a - - 1.200 - - 0.0472 a1 0.150 - - 0.0059 - - a2 - 0.200 - - 0.0079 - a4 - - 0.600 - - 0.0236 b 0.250 0.300 0.350 0.0098 0.0118 0.0138 d 4.850 5.000 5.150 0.1909 0.1969 0.2028 d1 - 3.500 - - 0.1378 - e 4.850 5.000 5.150 0.1909 0.1969 0.2028 e1 - 3.500 - - 0.1378 - e - 0.500 - - 0.0197 - f - 0.750 - - 0.0295 - ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 ( 6 0 6 y 9 ( q j l q h h u l q j v d p s o h p d u n l q j $ g g l w l r q d o l q i r u p d w l r q i l h o g l q f o x g l q j u h y l v l r q f r g h ' d w h f r g h < h d u z h h n < h d u : h h n 3 l q docid025938 rev 4 113/119 stm32l051x6 stm32l051x8 package characteristics 115 7.2 thermal characteristics the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max ja ) where: ? t a max is the maximum ambient temperature in c, ? ja is the package junction-to-ambient thermal resistance, in c/w, ? p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), ? p int max is the product of i dd and v dd , expressed in watts. th is is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = (v ol i ol ) + ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. table 79. thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient tfbga64 - 5 x 5 mm / 0.5 mm pitch 61 c/w thermal resistance junction-ambient lqfp64 - 10 x 10 mm / 0.5 mm pitch 45 thermal resistance junction-ambient wlcsp36 - 0.4 mm pitch 63 thermal resistance junction-ambient lqfp48 - 7 x 7 mm / 0.5 mm pitch 55 thermal resistance junction-ambient lqfp32 - 7 x 7 mm / 0.8 mm pitch 57 thermal resistance junction-ambient ufqfpn32 - 5 x 5 mm / 0.5 mm pitch 38 package characteristics stm32l051x6 stm32l051x8 114/119 docid025938 rev 4 figure 52. thermal resistance 7.2.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org. 0 6 y 9 ? ? ? ?? ? ?? e ?? ? ? ?? h y & e?? > y & we > y & we? > y & w?? d & ' e t > ^ w? 7 h p s h u d w x u h ? & 3 ' p : docid025938 rev 4 115/119 stm32l051x6 stm32l051x8 ordering information 115 8 ordering information for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 80. stm32l051x6/8 ordering information scheme example: stm32 l 051 r 8 t 6 d xxx device family stm32 = arm-based 32-bit microcontroller product type l = low power device subfamily 051 = access line pin count k = 32 pins t = 36 pins c = 48/49 pins r = 64 pins flash memory size 6 = 32 kbytes 8 = 64 kbytes package t = lqfp h = tfbga u = ufqfpn y = wlcsp pins temperature range 6 = industrial temperature range, ?40 to 85 c 7 = industrial temperature range, ?40 to 105 c 3 = industrial temperature range, ?40 to 125 c options no character = v dd range: 1.8 to 3.6 v and bor enabled d = v dd range: 1.65 to 3.6 v and bor disabled packing tr = tape and reel no character = tray or tube revision history stm32l051x6 stm32l051x8 116/119 docid025938 rev 4 9 revision history table 81. document revision history date revision changes 13-feb-2014 1 initial release. 29-apr-2014 2 added wlcsp36 package. updated table 2: ultra-low-power stm32l051x6/x8 device features and peripheral counts updated table 5: functionalities depending on the working mode (from run/active down to standby) . added section 3.2: interconnect matrix . updated figure 8: stm32l051x6/8 tfbga64 ballout - 5x 5 mm replaced tta i/o structure by tc , updated pa0/4/5, pc5/14, boot0 and nrst i/o structure in table 15: stm32l051x6/8 pin definitions . updated table 23: general operating conditions , table 20: voltage characteristics and table 21: current characteristics . modified conditions in table 26: embedded internal reference voltage . updated table 27: current consumption in run mode, code with data processing running from flash , table 29: current consumption in run mode, code with data processing running from ram , table 31: current consumption in sleep mode , table 32: current consumption in low- power run mode , table 33: current consumption in low-power sleep mode , table 34: typical and maximum current consumptions in stop mode and table 35: typical and maximum current consumptions in standby mode . added figure 14: idd vs vdd, at ta= 25/55/85/105 c, run mode, code running from flash memory, range 2, hse, 1ws , figure 15: idd vs vdd, at ta= 25/55/85/105 c, run mode, code running from flash memory, range 2, hsi16, 1ws , figure 16: idd vs vdd, at ta= 25 /55/ 85/105/125 c, low-power run mode, code running from ram, ran ge 3, msi (range 0) at 64 khz, 0 ws , figure 17: idd vs vdd, at ta= 25/55/ 85/105/125 c, stop mode with rtc enabled and running on lse low drive and figure 18: idd vs vdd, at ta= 25/55/ 85/105/125 c, stop mode with rtc disabled, all clocks off . updated table 42: hse oscillator characteristics and table 43: lse oscillator characteristics . added figure 23: hsi16 minimum and maximum value versus temperature . updated table 53: esd absolute maximum ratings , table 55: i/o current injectio n susceptibility and table 56: i/o static characteristics , and added figure 24: vih/vil versus vdd (cmos i/os) and figure 25: vih/vil versus vdd (ttl i/os) . updated table 57: output voltage characteristics , table 58: i/o ac characteristics and figure 26: i/o ac characteristics definition . updated table 60: adc characteristics , table 62: adc accuracy , and figure 29: typical connection diagram using the adc . updated table 64: temperature sensor characteristics . updated table 69: spi characteristics in voltage range 1 and table 72: i2s characteristics . added figure 52: thermal resistance . docid025938 rev 4 117/119 stm32l051x6 stm32l051x8 revision history 118 25-jun-2014 3 cover page: changed lqfp32 size, updated core speed. updated core speed, added minimum supply voltage for adc and comparators. adc now guaranteed down to 1.65 v. updated list of applications in section 1: introduction . changed number of i2s interfaces to one in section 2: description . updated table 2: ultra-low-power stm32l051x6/x8 device features and peripheral counts . updated table 3: functionalities depending on the operating power supply range . updated rtc/tim21 in table 6: stm32l0xx peripherals interconnect matrix . added note related to ufqfpn32 and note related to wlcsp36 in table 15: stm32l051x6/8 pin definitions . split lqfp32/ufqfpn32 pinout schematics into two distinct figures: figure 4 and figure 5 . updated v dda in table 23: general operating conditions . split table current consumption in run mode, code with data processing running from flash into table 27 and table 28 and content updated. split table current consumption in run mode, code with data processing running from ram into table 29 and table 30 and content updated. updated table 31: current consumption in sleep mode , table 32: current consumption in low-power run mode , table 33: current consumption in low-power sleep mode , table 34: typical and maximum current consumptions in stop mode , table 35: typical and maximum current consumptions in standby mode , and added table 36: average current consumption during wakeup . updated table 37: peripheral current consumption in run or sleep mode and added table 38: peripheral current consumption in stop and standby mode . updated t lock in table 47: pll characteristics . removed note 1 below figure 21: hse oscillator circuit diagram . updated table 49: flash memory and data eeprom characteristics and table 50: flash memory and data eeprom endurance and retention . updated table 58: i/o ac characteristics . updated table 60: adc characteristics . updated figure 52: thermal resistance and added note 1. table 81. document revision history (continued) date revision changes revision history stm32l051x6 stm32l051x8 118/119 docid025938 rev 4 05-sep-2104 4 extended operating temperature range to 125 c. updated minimum adc operating voltage to 1.65 v. updated section 3.4.1: power supply schemes . replaced usart3 by lpuart1 in table 15: stm32l051x6/8 pin definitions and lpuart by lpuart1 in table 16: alternate function port a , table 17: alternate function port b , table 18: alternate function port c and table 19: alternate function port d . updated temperature range in section 2: description , table 2: ultra- low-power stm32l051x6/x8 device features and peripheral counts . updated p d , t a and t j to add range 3 in table 23: general operating conditions . added range 3 in table 50: flash memory and data eeprom endurance and retention , table 80: stm32l051x6/8 ordering information scheme . update note 1 in table 27: current consumption in run mode, code with data processing running from flash , table 29: current consumption in run mode, code with data processing running from ram , table 31: current consumption in sleep mode , table 32: current consumption in low-power run mode , table 33: current consumption in low-power sleep mode , table 34: typical and maximum current consumptions in stop mode , table 35: typical and maximum current consumptions in standby mode and table 39: low-power mode wakeup timings . updated figure 52: thermal resistance and removed note 1. updated table 60: adc characteristics and table 62: adc accuracy . updated figure 16: idd vs vdd, at ta= 25/55/ 85/105/125 c, low- power run mode, code running from ram, range 3, msi (range 0) at 64 khz, 0 ws , figure 17: idd vs vdd, at ta= 25/55/ 85/105/125 c, stop mode with rtc enabled and running on lse low drive , figure 18: idd vs vdd, at ta= 25 /55/85/105/125 c, stop mode with rtc disabled, all clocks off . updated table 35: typical and maximum current consumptions in standby mode . updated syscfg in table 37: peripheral current consumption in run or sleep mode . updated table 38: peripheral current consumption in stop and standby mode and table 39: low-power mode wakeup timings . updated acc hsi16 temperature conditions in table 44: 16 mhz hsi16 oscillator characteristics . updated v f(nrst) and v nf(nrst) in table 59: nrst pin characteristics . updated table 60: adc characteristics and table 62: adc accuracy . added range 3 in table 80: stm32l051x6/8 ordering information scheme . table 81. document revision history (continued) date revision changes docid025938 rev 4 119/119 stm32l051x6 stm32l051x8 119 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved |
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